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公开(公告)号:US11494629B2
公开(公告)日:2022-11-08
申请号:US16669855
申请日:2019-10-31
发明人: Zhongze Wang , Xia Li , Xiaochun Zhu
IPC分类号: G11C16/08 , G06N3/063 , G11C11/419 , G11C11/412 , G11C11/21
摘要: Certain aspects provide a circuit for in-memory computation. The circuit generally includes a first memory cell, and a first computation circuit. The first computation circuit may include a first switch having a control input coupled to an output of the first memory cell, a second switch coupled between a node of the first computation circuit and the first switch, a control input of the second switch being coupled to a discharge word-line (DCWL), a capacitive element coupled between the node and a reference potential node, a third switch coupled between the node and a read bit-line (RBL), and a fourth switch coupled between the node and an activation (ACT) line.
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公开(公告)号:US11037942B2
公开(公告)日:2021-06-15
申请号:US16743088
申请日:2020-01-15
IPC分类号: H01L27/115 , H01L27/11507 , H01L49/02 , H01L27/11514 , G11C11/21 , G11C11/24
摘要: A memory cell includes a first electrode and a second electrode. A select device and a programmable device are in series with each other between the first and second electrodes. The select device is proximate and electrically coupled to the first electrode. The programmable device is proximate and electrically coupled to the second electrode. The programmable device includes a radially inner electrode having radially outer sidewalls. Ferroelectric material is radially outward of the outer sidewalls of the inner electrode. A radially outer electrode is radially outward of the ferroelectric material. One of the outer electrode or the inner electrode is electrically coupled to the select device. The other of the outer electrode and the inner electrode is electrically coupled to the second electrode. Arrays of memory cells are disclosed.
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公开(公告)号:US11011226B2
公开(公告)日:2021-05-18
申请号:US16838423
申请日:2020-04-02
摘要: Systems, integrated circuits, and methods to utilize access signals to facilitate memory operations in scaled arrays of memory elements are described. In at least some embodiments, a non-volatile memory device can include a cross-point array having resistive memory elements and line driver. The line driver can be configured to access a resistive memory element in the cross-point array.
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公开(公告)号:US20200335144A1
公开(公告)日:2020-10-22
申请号:US16869816
申请日:2020-05-08
摘要: Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement circuits configured to compensate for parameter variations in layers of memory by adjusting access signals during memory operations. In some embodiments, memory cells are based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes multiple layers of memory, a layer including sub-layers of semiconductor material. The integrated circuit also includes an access signal generator configured to generate an access signal to facilitate an access operation, and a characteristic adjuster configured to adjust the access signal for each layer in the multiple layers of memory.
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公开(公告)号:US20200303005A1
公开(公告)日:2020-09-24
申请号:US16838423
申请日:2020-04-02
摘要: Systems, integrated circuits, and methods to utilize access signals to facilitate memory operations in scaled arrays of memory elements are described. In at least some embodiments, a non-volatile memory device can include a cross-point array having resistive memory elements and line driver. The line driver can be configured to access a resistive memory element in the cross-point array.
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公开(公告)号:US20200013460A1
公开(公告)日:2020-01-09
申请号:US16511205
申请日:2019-07-15
摘要: Systems, integrated circuits, and methods to utilize access signals to facilitate memory operations in scaled arrays of memory elements are described. In at least some embodiments, a non-volatile memory device can include a cross-point array having resistive memory elements and line driver. The line driver can be configured to access a resistive memory element in the cross-point array.
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公开(公告)号:US10529424B2
公开(公告)日:2020-01-07
申请号:US16274521
申请日:2019-02-13
发明人: Yuniarto Widjaja
IPC分类号: G11C11/24 , G11C14/00 , G11C11/404 , H01L29/78 , H01L27/108 , G11C11/4072 , G11C13/00 , H01L45/00 , H01L27/24 , G11C11/21 , G11C11/407
摘要: A semiconductor memory cell including a capacitorless transistor having a floating body configured to store data as charge therein when power is applied to the cell, and a non-volatile memory comprising a bipolar resistive change element, and methods of operating.
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公开(公告)号:US20190180820A1
公开(公告)日:2019-06-13
申请号:US16274521
申请日:2019-02-13
发明人: Yuniarto Widjaja
IPC分类号: G11C14/00 , G11C11/407 , G11C11/21 , G11C13/00 , H01L45/00 , H01L27/24 , H01L27/108 , H01L29/78 , G11C11/404 , G11C11/4072
CPC分类号: G11C14/0045 , G11C11/21 , G11C11/404 , G11C11/407 , G11C11/4072 , G11C13/00 , G11C13/0004 , G11C13/0007 , G11C13/0069 , G11C14/00 , G11C14/0027 , G11C14/0036 , G11C14/009 , G11C2013/0073 , H01L27/10802 , H01L27/1085 , H01L27/10879 , H01L27/2436 , H01L29/7841 , H01L45/00 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/146 , H01L45/147
摘要: A semiconductor memory cell including a capacitorless transistor having a floating body configured to store data as charge therein when power is applied to the cell, and a non-volatile memory comprising a bipolar resistive change element, and methods of operating.
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公开(公告)号:US09927391B2
公开(公告)日:2018-03-27
申请号:US15244991
申请日:2016-08-23
申请人: Bao Tran
发明人: Bao Tran
IPC分类号: H01L47/00 , G01N27/414 , H01L45/00 , G11C11/21 , G11B9/14 , G11C11/54 , G11C13/02 , G11C13/04 , H01L51/42 , G11C13/00 , H01L27/24 , B82Y10/00 , B82Y15/00 , B82Y40/00
CPC分类号: G01N33/0034 , B82Y10/00 , B82Y15/00 , B82Y40/00 , G01N27/122 , G01N27/128 , G01N27/4146 , G01N27/4148 , G11B9/14 , G11C11/21 , G11C11/54 , G11C13/0023 , G11C13/004 , G11C13/02 , G11C13/04 , H01L27/2463 , H01L45/12 , H01L45/1233 , H01L45/1253 , H01L45/16 , H01L51/4226 , H01L51/4253 , Y02E10/549 , Y10S977/762 , Y10S977/775 , Y10S977/938 , Y10S977/957
摘要: A device includes an upper metallic layer, a lower layer, and a nano sensor array positioned between the upper and lower layers to detect a presence of a gas, a chemical, or a biological object, wherein each sensor's electrical characteristic changes when encountering the gas, chemical or biological object.
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公开(公告)号:US09666275B2
公开(公告)日:2017-05-30
申请号:US15191137
申请日:2016-06-23
发明人: Yuniarto Widjaja
IPC分类号: G11C11/00 , G11C14/00 , G11C11/21 , G11C11/404 , G11C13/00 , H01L29/78 , H01L45/00 , H01L27/108 , G11C11/4072 , H01L27/24 , G11C11/407
CPC分类号: G11C14/0045 , G11C11/21 , G11C11/404 , G11C11/407 , G11C11/4072 , G11C13/00 , G11C13/0004 , G11C13/0007 , G11C13/0069 , G11C14/00 , G11C14/0027 , G11C14/0036 , G11C14/009 , G11C2013/0073 , H01L27/10802 , H01L27/1085 , H01L27/10879 , H01L27/2436 , H01L29/7841 , H01L45/00 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/146 , H01L45/147
摘要: A semiconductor memory cell including a capacitorless transistor having a floating body configured to store data as charge therein when power is applied to the cell, and a non-volatile memory comprising a bipolar resistive change element, and methods of operating.
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