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    MEMORY DEVICE USING SEMICONDUCTOR ELEMENT
    1.
    发明公开
    MEMORY DEVICE USING SEMICONDUCTOR ELEMENT 审中-公开

    公开(公告)号：US20240349482A1

    公开(公告)日：2024-10-17

    申请号：US18624515

    申请日：2024-04-02

    Applicant: Unisantis Electronics Singapore Pte. Ltd.

    Inventor： Masakazu KAKUMU ,  Koji SAKUI ,  Nozomu HARADA

    IPC: H10B12/00 ,  G11C11/404 ,  G11C11/4096

    CPC classification number: H10B12/20 ,  G11C11/404 ,  G11C11/4096

    Abstract: Provided is a memory semiconductor device including an access transistor, in which an n-type semiconductor layer is formed on a p-type semiconductor region provided on a substrate; a first p-type semiconductor layer that has a columnar shape exists in a vertical direction from a portion of the n-type semiconductor layer; an insulating layer that covers a portion of the first p-type semiconductor layer and a portion of the n-type semiconductor layer exists; in contact therewith, a first gate insulating layer contacts the first p-type semiconductor layer; in contact with the first gate insulating layer, a first gate conductive layer exists; a second p-type semiconductor layer whose surface is recessed exists on the first p-type semiconductor layer; a second gate insulating layer and a second gate conductive layer exist thereabove; and an n+ layer is provided on both sides thereof.

    Memory device through use of semiconductor device
    2.
    发明授权
    Memory device through use of semiconductor device 有权

    公开(公告)号：US12108589B2

    公开(公告)日：2024-10-01

    申请号：US17741914

    申请日：2022-05-11

    Applicant: Unisantis Electronics Singapore Pte. Ltd.

    Inventor： Koji Sakui ,  Nozomu Harada

    IPC: G11C11/40 ,  G11C11/404 ,  G11C11/4096 ,  H10B12/00

    CPC classification number: H10B12/20 ,  G11C11/404 ,  G11C11/4096

    Abstract: A memory device includes pages, each being composed of a plurality of memory cells arrayed on a substrate in row form. The memory device controls voltages to be applied to a first gate conductor layer, a second gate conductor layer, a first impurity region, and a second impurity region of each of the memory cells included in the pages to perform a page write operation of holding a hole group formed by an impact ionization phenomenon or a gate induced drain leakage current in a channel semiconductor layer, and controls voltages to be applied to the first gate conductor layer, the second gate conductor layer, the third gate conductor layer, the fourth gate conductor layer, the first impurity region, and the second impurity region to perform a page erase operation of removing the hole group out of the channel semiconductor layer. The first impurity layer of each of the memory cells is connected to a source line, the second impurity region is connected to a bit line, one of the first gate conductor layer and the second gate conductor layer is connected to a word line, and the other is connected to a first driving control line. The bit line is connected to a sense amplifier circuit via a switching circuit. When in a page read operation, the memory device reads page data in a memory cell group selected by the word line to the bit line, and performs charge sharing between the bit line and a charge sharing node of the switching circuit opposite to the bit line to accelerate a read determination by the sense amplifier circuit.

    MEMORY DEVICE USING SEMICONDUCTOR ELEMENT
    3.
    发明公开
    MEMORY DEVICE USING SEMICONDUCTOR ELEMENT 审中-公开

    公开(公告)号：US20240206151A1

    公开(公告)日：2024-06-20

    申请号：US18545216

    申请日：2023-12-19

    Applicant: Unisantis Electronics Singapore Pte. Ltd.

    Inventor： Koji SAKUI ,  Masakazu KAKUMU ,  Nozomu HARADA

    IPC: H10B12/00 ,  G11C11/404 ,  G11C11/4096

    CPC classification number: H10B12/20 ,  G11C11/404 ,  G11C11/4096

    Abstract: A memory device includes at least one memory array made up of pages and bit lines. Each page includes multiple memory cells connected to a bit line. A plate line is connected to a first gate conductor layer, a source line is connected to an n+ layer, the bit line is connected to an n+ layer, and a word line is connected to a second gate conductor layer. A write operation of holding positive hole groups near a gate insulating layer and an erase operation of removing the positive hole groups are performed by controlling voltages applied to the source line, the bit line, the word line, the plate line, and the bottom line, where the positive hole groups are generated in a channel region of a third semiconductor layer by a gate induced drain leakage current.

    MEMORY-ELEMENT-INCLUDING SEMICONDUCTOR DEVICE
    6.
    发明公开
    MEMORY-ELEMENT-INCLUDING SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20240179887A1

    公开(公告)日：2024-05-30

    申请号：US18520130

    申请日：2023-11-27

    Applicant: Unisantis Electronics Singapore Pte. Ltd.

    Inventor： Nozomu HARADA ,  Masakazu KAKUMU ,  Koji SAKUI

    IPC: H10B12/00 ,  G11C11/404 ,  G11C11/4096

    CPC classification number: H10B12/20 ,  G11C11/404 ,  G11C11/4096

    Abstract: In a memory cell including a first gate insulating layer 5 and a first gate conductor layer 6 surrounding a P layer 3a constituting a lower portion of a pillar-shaped P layer 3 standing on a P layer substrate 1, a second gate insulating layer 9 surrounding a P layer 3b constituting an upper portion of the P layer 3, a second gate conductor layer 10, and N+ layers 11a and 11b at both ends of the P layer 3b and a MOS transistor including a pillar-shaped P layer 3A standing on a P layer substrate 1a connecting to the same P layer substrate 1, a third gate insulating layer 9a surrounding an upper P layer 3ba of the P layer 3A, a third gate conductor layer 10a, and N+ layers 11aa and 11ba at both ends of the P layer 3ba, bottom portions and top portions of the P layer 3 and the P layer 3A are located at substantially the same heights of line A and line C, respectively, in a perpendicular direction, and bottom portions of the P layer 3b and the P layer 3ba are located at substantially the same height of line B.

    MEMORY DEVICE INCLUDING SEMICONDUCTOR ELEMENT
    10.
    发明公开
    MEMORY DEVICE INCLUDING SEMICONDUCTOR ELEMENT 审中-公开

    公开(公告)号：US20240098968A1

    公开(公告)日：2024-03-21

    申请号：US18470090

    申请日：2023-09-19

    Applicant: Unisantis Electronics Singapore Pte. Ltd.

    Inventor： Nozomu HARADA ,  Koji SAKUI

    IPC: H10B12/00 ,  G11C11/404 ,  G11C11/4096

    CPC classification number: H10B12/20 ,  G11C11/404 ,  G11C11/4096

    Abstract: A first N+ layer, a first P layer, a second N+ layer, a second P layer, and a third N+ layer are formed on a P layer substrate in order from below vertically, a first gate insulating layer surrounds the first P layer, a second gate insulating layer surrounds the second P layer, first and second gate conductor layers surround the first gate insulating layer, and third and fourth gate conductor layers surround the second gate insulating layer. A first wiring layer is connected to the first N+ layer, a second wiring layer is connected to the second N+ layer, and a third wiring layer is connected to the third N+ layer. The first and second gate conductor layers, the second wiring layer, and the third and fourth gate conductor layers have identical shapes in a plan view and are orthogonal to the first and third wiring layers.

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