公开(公告)号：US10978455B2

公开(公告)日：2021-04-13

申请号：US16827373

申请日：2020-03-23

申请人： Zeno Semiconductor, Inc.

发明人： Yuniarto Widjaja ,  Jin-Woo Han ,  Benjamin S. Louie

IPC分类号： G11C11/404 ,  H01L27/102 ,  H01L27/108 ,  H01L29/78 ,  H01L29/70 ,  H01L29/73 ,  G11C16/04 ,  G11C16/10 ,  H01L27/11524 ,  H01L29/08 ,  H01L29/10 ,  H01L29/36 ,  G11C16/26 ,  G11C16/34 ,  H01L29/732

摘要： A semiconductor memory cell includes a floating body region configured to be charged to a level indicative of a state of the memory cell selected from at least first and second states. A first region of the memory cell is in electrical contact with the floating body region. A second region of the memory cell is spaced apart from the first region and is also in electrical contact with the floating body region. A gate is positioned between the first and second regions. A back-bias region is configured to generate impact ionization when the memory cell is in one of the first and second states, and the back-bias region is configured so as not to generate impact ionization when the memory cell is in the other of the first and second states.

公开(公告)号：US10861941B2

公开(公告)日：2020-12-08

申请号：US16286648

申请日：2019-02-27

申请人： KABUSHIKI KAISHA TOSHIBA

发明人： Akira Kano ,  Akihiro Goryu ,  Kenji Hirohata

IPC分类号： H01L29/16 ,  H01L29/70 ,  H01L21/02

摘要： According to an embodiment, in a semiconductor device, a total value of a change amount of chemical potential of the semiconductor device with respect to a expansion direction of a stacking fault and the stacking fault energy of the stacking fault is zero or more.

公开(公告)号：US10418471B2

公开(公告)日：2019-09-17

申请号：US15486921

申请日：2017-04-13

申请人： Ideal Power, Inc.

发明人： William C. Alexander ,  Richard A. Blanchard

IPC分类号： H01L29/747 ,  H01L29/40 ,  H01L29/423 ,  H01L29/732 ,  H01L29/06 ,  H01L29/10 ,  H03K17/66 ,  H01L29/70

摘要： Dual-base two-sided bipolar power transistors which use an insulated field plate to separate the emitter/collector diffusions from the nearest base contact diffusion. This provides a surprising improvement in turn-off performance, and in breakdown voltage.

公开(公告)号：US09991316B2

公开(公告)日：2018-06-05

申请号：US15374304

申请日：2016-12-09

申请人： STMICROELECTRONICS S.R.L.

发明人： Paola Zuliani ,  Gianluigi Confalonieri ,  Annalisa Gilardini ,  Carlo Luigi Prelini

IPC分类号： H01L29/70 ,  H01L45/00 ,  H01L27/24

CPC分类号： H01L27/2463 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/1293 ,  H01L45/144 ,  H01L45/16 ,  H01L45/1683

摘要： A phase-change memory cell, comprising: a substrate housing a transistor, for selection of the memory cell, that includes a first conduction electrode; a first electrical-insulation layer on the selection transistor; a first conductive through via through the electrical-insulation layer electrically coupled to the first conduction electrode; a heater element including a first portion in electrical contact with the first conductive through via and a second portion that extends in electrical continuity with, and orthogonal to, the first portion; a first protection element extending on the first and second portions of the heater element; a second protection element extending in direct lateral contact with the first portion of the heater element and with the first protection element; and a phase-change region extending over the heater element in electrical and thermal contact therewith.

公开(公告)号：US09917180B2

公开(公告)日：2018-03-13

申请号：US15114263

申请日：2015-02-10

申请人： UNITED SILICON CARBIDE, INC.

发明人： Anup Bhalla ,  Leonid Fursin

IPC分类号： H01L29/70 ,  H01L29/732 ,  H01L29/423 ,  H01L29/66 ,  H01L29/872 ,  H01L29/10 ,  H01L29/16 ,  H01L29/20 ,  H01L29/73 ,  H01L29/861 ,  H01L29/06 ,  H01L27/06

CPC分类号： H01L29/732 ,  H01L27/0664 ,  H01L29/0619 ,  H01L29/1004 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/42304 ,  H01L29/66068 ,  H01L29/66272 ,  H01L29/66295 ,  H01L29/6631 ,  H01L29/73 ,  H01L29/8611 ,  H01L29/872

摘要： The present invention concerns a monolithically merged trenched-and-implanted Bipolar Junction Transistor (TI-BJT) with antiparallel diode and a method of manufacturing the same. Trenches are made in a collector, base, emitter stack downto the collector. The base electrode is formed on an implanted base contact region at the bottom surface of the trench. The present invention also provides for products produced by the methods of the present invention and for apparatuses used to perform the methods of the present invention.

公开(公告)号：US09576962B2

公开(公告)日：2017-02-21

申请号：US14955339

申请日：2015-12-01

申请人： Zeno Semiconductor, Inc.

发明人： Yuniarto Widjaja ,  Jin-Woo Han ,  Benjamin S. Louie

IPC分类号： H01L27/108 ,  H01L29/08 ,  H01L29/78 ,  H01L29/70 ,  G11C11/404 ,  G11C16/04 ,  G11C16/10 ,  H01L27/115 ,  H01L27/102 ,  H01L29/10 ,  H01L29/73

CPC分类号： H01L27/10802 ,  G11C11/404 ,  G11C16/0433 ,  G11C16/10 ,  G11C16/26 ,  G11C16/3427 ,  H01L27/1023 ,  H01L27/11524 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/1095 ,  H01L29/36 ,  H01L29/70 ,  H01L29/73 ,  H01L29/7302 ,  H01L29/732 ,  H01L29/7841

摘要： A semiconductor memory cell includes a floating body region configured to be charged to a level indicative of a state of the memory cell selected from at least first and second states. A first region of the memory cell is in electrical contact with the floating body region. A second region of the memory cell is spaced apart from the first region and is also in electrical contact with the floating body region. A gate is positioned between the first and second regions. A back-bias region is configured to generate impact ionization when the memory cell is in one of the first and second states, and the back-bias region is configured so as not to generate impact ionization when the memory cell is in the other of the first and second states.

摘要翻译： 半导体存储单元包括被配置为被充电到指示从至少第一和第二状态中选择的存储单元的状态的电平的浮动体区域。 存储单元的第一区域与浮体区域电接触。 存储单元的第二区域与第一区域间隔开并且还与浮体区域电接触。 门位于第一和第二区之间。 背偏置区域被配置为当存储器单元处于第一和第二状态之一时产生冲击电离，并且背偏置区被配置为当存储单元位于另一个状态时不产生碰撞电离 第一和第二州。

公开(公告)号：US09281375B2

公开(公告)日：2016-03-08

申请号：US14313114

申请日：2014-06-24

申请人： Xin Lin ,  Bernhard H. Grote ,  Jiang-Kai Zuo

发明人： Xin Lin ,  Bernhard H. Grote ,  Jiang-Kai Zuo

IPC分类号： H01L21/331 ,  H01L29/73 ,  H01L29/66 ,  H01L21/8222 ,  H01L21/8249 ,  H01L29/735 ,  H01L29/70

CPC分类号： H01L29/6625 ,  H01L21/8222 ,  H01L21/8249 ,  H01L29/705 ,  H01L29/7317 ,  H01L29/735

摘要： Methods for producing bipolar transistors are provided. In one embodiment, the method includes producing a bipolar transistor including first and second connected emitter-base (EB) junctions of varying different depths. A buried layer (BL) collector is further produced to have a third depth greater than the depths of the EB junctions. The emitters and bases corresponding to the different EB junctions are provided during a chain implant. An isolation region may overlie the second EB junction location. The BL collector is laterally spaced from the first EB junction by a variable amount to facilitate adjustment of the transistor properties. The BL collector may or may not underlie at least a portion of the second EB junction. Regions of opposite conductivity type overlie and underlie the BL collector to preserve breakdown voltage. The transistor can be readily “tuned” by mask adjustments alone to meet various device requirements.

摘要翻译： 提供了制造双极晶体管的方法。 在一个实施例中，该方法包括产生包括变化不同深度的第一和第二连接的发射极基极（EB）结的双极晶体管。 进一步制造掩埋层（BL）集电体以具有大于EB结的深度的第三深度。 在链植入期间提供对应于不同EB结的发射器和基座。 隔离区域可以覆盖第二EB结点位置。 BL收集器与第一EB结横向间隔可变量以便于调整晶体管特性。 BL收集器可以或可以不位于第二EB结的至少一部分的下面。 相反导电类型的区域叠加在BL集电极之下，以保持击穿电压。 晶体管可以通过单独的掩模调节容易地“调谐”以满足各种器件要求。

公开(公告)号：US09230651B2

公开(公告)日：2016-01-05

申请号：US13746523

申请日：2013-01-22

申请人： Yuniarto Widjaja ,  Jin-Woo Han ,  Benjamin S. Louie

发明人： Yuniarto Widjaja ,  Jin-Woo Han ,  Benjamin S. Louie

IPC分类号： H01L29/78 ,  H01L29/70 ,  G11C16/04 ,  G11C11/404 ,  H01L27/108 ,  G11C16/10 ,  H01L27/115

CPC分类号： H01L27/10802 ,  G11C11/404 ,  G11C16/0433 ,  G11C16/10 ,  G11C16/26 ,  G11C16/3427 ,  H01L27/1023 ,  H01L27/11524 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/1095 ,  H01L29/36 ,  H01L29/70 ,  H01L29/73 ,  H01L29/7302 ,  H01L29/732 ,  H01L29/7841

摘要： A semiconductor memory cell includes a floating body region configured to be charged to a level indicative of a state of the memory cell selected from at least first and second states. A first region of the memory cell is in electrical contact with the floating body region. A second region of the memory cell is spaced apart from the first region and is also in electrical contact with the floating body region. A gate is positioned between the first and second regions. A back-bias region is configured to generate impact ionization when the memory cell is in one of the first and second states, and the back-bias region is configured so as not to generate impact ionization when the memory cell is in the other of the first and second states.

摘要翻译： 半导体存储单元包括被配置为被充电到指示从至少第一和第二状态中选择的存储单元的状态的电平的浮动体区域。 存储单元的第一区域与浮体区域电接触。 存储单元的第二区域与第一区域间隔开并且还与浮体区域电接触。 门位于第一和第二区之间。 背偏置区域被配置为当存储器单元处于第一和第二状态之一时产生冲击电离，并且背偏置区被配置为当存储单元位于另一个状态时不产生碰撞电离 第一和第二州。

公开(公告)号：US09099397B1

公开(公告)日：2015-08-04

申请号：US13427097

申请日：2012-03-22

申请人： James Chingwei Li

发明人： James Chingwei Li

IPC分类号： H01L21/306 ,  H01L21/265 ,  H01L21/285 ,  H01L29/70 ,  H01L27/102 ,  H01L31/11

CPC分类号： H01L21/306 ,  H01L21/265 ,  H01L21/285 ,  H01L27/102 ,  H01L29/401 ,  H01L29/42304 ,  H01L29/6625 ,  H01L29/70 ,  H01L29/732 ,  H01L29/7371 ,  H01L31/11

摘要： A transistor includes a first emitter layer area, a second emitter layer area, wherein the second emitter layer area is separate from the first emitter layer area, a first metal formed on the first emitter layer area, a second metal formed on the second emitter layer area, a base, and a base metal formed on the base and on the second metal. The first emitter layer area is an emitter of the transistor and the first metal provides an emitter contact. The base metal on the base and on the second metal provides a base contact.

摘要翻译： 晶体管包括第一发射极层区域，第二发射极层区域，其中第二发射极层区域与第一发射极层区域分离，形成在第一发射极层区域上的第一金属，形成在第二发射极层上的第二金属 区域，基部和形成在基部和第二金属上的基底金属。 第一发射极层区域是晶体管的发射极，第一金属提供发射极接触。 底座上的第二金属和第二金属上的母材提供了底座接触。

公开(公告)号：US08841698B2

公开(公告)日：2014-09-23

申请号：US13078510

申请日：2011-04-01

申请人： Philip G. Neudeck

发明人： Philip G. Neudeck

IPC分类号： H01L29/66 ,  H01L29/70 ,  H01L29/808 ,  H01L21/04 ,  H01L29/08 ,  H01L29/16 ,  H01L29/20

CPC分类号： H01L29/808 ,  H01L21/046 ,  H01L21/0465 ,  H01L21/0475 ,  H01L21/26593 ,  H01L29/0843 ,  H01L29/1602 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/66068 ,  H01L29/66901 ,  H01L29/66916

摘要： A method is disclosed that provides a self-aligned nitrogen-implant particularly suited for a Junction Field Effect Transistor (JFET) semiconductor device preferably comprised of a silicon carbide (SiC). This self-aligned nitrogen-implant allows for the realization of durable and stable electrical functionality of high temperature transistors such as JFETs. The method implements the self-aligned nitrogen-implant having predetermined dimensions, at a particular step in the fabrication process, so that the SiC junction field effect transistors are capable of being electrically operating continuously at 500° C. for over 10,000 hours in an air ambient with less than a 10% change in operational transistor parameters.

摘要翻译： 公开了一种提供特别适合于优选由碳化硅（SiC）构成的结型场效应晶体管（JFET）半导体器件的自对准氮注入的方法。 这种自对准氮 - 注入允许实现高温晶体管（例如JFET）的耐用且稳定的电功能。 该方法在制造过程的特定步骤中实现具有预定尺寸的自对准氮注入，使得SiC结场效应晶体管能够在500℃下连续电连续工作，在空气中超过10,000小时 环境中运行晶体管参数的变化小于10％。