公开(公告)号：US20240355922A1

公开(公告)日：2024-10-24

申请号：US18413662

申请日：2024-01-16

Applicant: Mitsubishi Electric Corporation

Inventor： Katsutoshi SUGAWARA ,  Kotaro KAWAHARA ,  Akifumi IIJIMA ,  Shiro HINO ,  Katsuhiro FUJIYOSHI

IPC: H01L29/78 ,  H01L21/04 ,  H01L29/06 ,  H01L29/08 ,  H01L29/16 ,  H01L29/66 ,  H02P27/08

CPC classification number: H01L29/7806 ,  H01L21/046 ,  H01L29/063 ,  H01L29/086 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7813 ,  H02P27/08

Abstract: A semiconductor device includes: a drift layer of a first conductivity type; well layers of a second conductivity type; a source layer of a first conductivity type; a gate electrode; an interlayer insulating film; and a source electrode, in which a plurality of body diodes constituted by the well layer and the drift layer at positions not overlapping with the gate electrode in plan view include a first operation portion that operates at a first body diode operation voltage and a plurality of second operation portions that operate at a second body diode operation voltage lower than the first body diode operation voltage.

公开(公告)号：US20240339323A1

公开(公告)日：2024-10-10

申请号：US18587742

申请日：2024-02-26

Applicant: FUJI ELECTRIC CO., LTD.

Inventor： Atsushi YOSHIMOTO ,  Hidenori SATOU ,  Takahito KOJIMA

IPC: H01L21/04 ,  H01L29/06 ,  H01L29/16 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/0475 ,  H01L21/046 ,  H01L29/063 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7813

Abstract: A method of manufacturing a silicon carbide semiconductor device, includes preparing a silicon carbide semiconductor substrate in which a first semiconductor layer of a first conductivity type is provided on a starting substrate of the first conductivity type; ion-implanting first semiconductor regions of a second conductivity type in the first semiconductor layer; thereafter, forming, at a C-face, an oxide film thicker than that at a Si-face as a treatment of reversing warpage of the silicon carbide semiconductor substrate. The method further includes ion-implanting a second semiconductor layer of the second conductivity type in the first semiconductor layer and a third semiconductor layer of the first conductivity type in a surface layer of the second semiconductor layer; activating the first semiconductor regions and the second and third semiconductor layers; and forming trenches reaching the first semiconductor layer at positions facing the first semiconductor regions in a depth direction.

公开(公告)号：US20240339322A1

公开(公告)日：2024-10-10

申请号：US18564501

申请日：2022-04-26

Applicant: Hitachi Energy Ltd

Inventor： Giovanni ALFIERI ,  Lars KNOLL

IPC: H01L21/04 ,  H01L29/16 ,  H01L29/66 ,  H01L29/73 ,  H01L29/739 ,  H01L29/868 ,  H01L29/872

CPC classification number: H01L21/047 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/73 ,  H01L29/7393 ,  H01L29/868 ,  H01L29/872

Abstract: The present disclosure relates to a semiconductor device (1) comprising at least one epitaxial layer (2) made from a first semiconductor material comprising carbon and having a [0001] crystallographic axis. At least one implantation area (4) is formed at a sidewall (3a) of the epitaxial layer (2), wherein a normal direction of the sidewall (3a) is perpendicular to the [0001] crystallographic axis. At least one part of the epitaxial layer (2) has a reduced concentration of carbon vacancy (VC) with respect to the first semiconductor material of the at least one epitaxial layer (2) as-grown. The present disclosure further relates to a method for manufacturing a semiconductor device (1), wherein ions are implanted through at least one sidewall (3a) of at least one epitaxial layer (2).

公开(公告)号：US20240332364A1

公开(公告)日：2024-10-03

申请号：US18573490

申请日：2022-06-15

Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.

Inventor： Taro NISHIGUCHI

IPC: H01L29/16 ,  H01L21/02 ,  H01L29/34 ,  H01L29/36 ,  H01L29/66

CPC classification number: H01L29/1608 ,  H01L21/02378 ,  H01L21/02529 ,  H01L29/34 ,  H01L29/36 ,  H01L29/66068

Abstract: A silicon carbide epitaxial substrate includes a silicon carbide substrate, a silicon carbide epitaxial layer, and a bump. The silicon carbide epitaxial layer is located on the silicon carbide substrate. The bump is formed on the silicon carbide epitaxial layer. The silicon carbide epitaxial layer includes a main surface located opposite to a boundary surface between the silicon carbide substrate and the silicon carbide epitaxial layer, and a drift layer that constitutes the main surface. An area density of the bump is 1.0/cm2 or less on the main surface. A height of the bump is 50 nm or more. A diameter of the bump is 5 μm or more and 30 μm or less. A polytype of silicon carbide of the bump is the same as a polytype of silicon carbide of the silicon carbide epitaxial layer.

公开(公告)号：US20240304447A1

公开(公告)日：2024-09-12

申请号：US18652013

申请日：2024-05-01

Applicant: ROHM CO., LTD.

Inventor： Yuki NAKANO

IPC: H01L21/04 ,  H01L21/02 ,  H01L21/28 ,  H01L27/04 ,  H01L29/06 ,  H01L29/10 ,  H01L29/16 ,  H01L29/20 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H01L29/861 ,  H01L29/872

CPC classification number: H01L21/049 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/02241 ,  H01L21/02255 ,  H01L21/02271 ,  H01L21/044 ,  H01L21/28008 ,  H01L21/28264 ,  H01L27/04 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/1602 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66045 ,  H01L29/6606 ,  H01L29/66068 ,  H01L29/66446 ,  H01L29/7806 ,  H01L29/7813 ,  H01L29/8611 ,  H01L29/872 ,  H01L2224/0603

Abstract: A method for producing a semiconductor power device includes forming a gate trench from a surface of the semiconductor layer toward an inside thereof. A first insulation film is formed on the inner surface of the gate trench. The method also includes removing a part on a bottom surface of the gate trench in the first insulation film. A second insulation film having a dielectric constant higher than SiO2 is formed in such a way as to cover the bottom surface of the gate trench exposed by removing the first insulation film.

公开(公告)号：US12087852B2

公开(公告)日：2024-09-10

申请号：US17290145

申请日：2019-10-30

Applicant: AIR WATER INC.

Inventor： Shigeomi Hishiki ,  Keisuke Kawamura

IPC: H01L29/778 ,  H01L29/10 ,  H01L29/267 ,  H01L29/66 ,  H01L29/16 ,  H01L29/167 ,  H01L29/20 ,  H01L29/205

CPC classification number: H01L29/7786 ,  H01L29/1075 ,  H01L29/267 ,  H01L29/66068 ,  H01L29/66462 ,  H01L29/1608 ,  H01L29/167 ,  H01L29/2003 ,  H01L29/205

Abstract: A compound semiconductor device, a compound semiconductor substrate, and a method for manufacturing of a compound semiconductor device. Compound semiconductor device 100 comprises Si substrate 1 which has a shape surrounding hole 21 when viewed in a plane, SIC layer 3 formed on top surface 1a of Si substrate 1 and covers hole 21, nitride layer 10 containing Ga formed on the top surface side of SiC layer 3, source electrode 13, drain electrode 15, and gate electrode 17 formed on the top surface side of nitride layer 10. The current flowing between source electrode 13 and drain electrode 15 can be controlled by the voltage applied to gate electrode 17. The Si substrate does not exist in the area RG where source electrode 13, drain electrode 15, and gate electrode 17 overlap the area when viewed from the direction orthogonal to top surface 1a of Si substrate 1.

公开(公告)号：US20240297043A1

公开(公告)日：2024-09-05

申请号：US18583758

申请日：2024-02-21

Applicant: STMicroelectronics International N.V.

Inventor： Alfio GUARNERA ,  Cateno Marco CAMALLERI ,  Edoardo ZANETTI ,  Laura Letizia SCALIA ,  Mario Pietro BERTOLINI ,  Massimiliano CANTIANO ,  Massimo BOSCAGLIA ,  Mario Giuseppe SAGGIO

IPC: H01L21/04 ,  H01L29/06 ,  H01L29/10 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/046 ,  H01L29/0619 ,  H01L29/1037 ,  H01L29/1095 ,  H01L29/66068 ,  H01L29/7802

Abstract: A process for manufacturing a power electronic device, envisages: forming a semiconductor body of silicon carbide, having a first electrical conductivity and a first doping value, and defining a front surface; forming a Current Spreading Layer, CSL, in a surface portion of said semiconductor body facing the front surface, having the first electrical conductivity and a second doping value, greater than the first doping value; forming elementary cells of the power electronic device in an active area of the semiconductor body at the front surface. The step of forming the current spreading layer envisages performing a channeled ion implantation, in a channeling condition, for implanting doping ions having the first electrical conductivity within the semiconductor body.

公开(公告)号：US20240282810A1

公开(公告)日：2024-08-22

申请号：US18571176

申请日：2022-10-18

Applicant: HUBEI JIUFENGSHAN LABORATORY

Inventor： Jun YUAN

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/16 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/0623 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7813

Abstract: A SiC MOSFET device and a method for manufacturing the same. The SiC MOSFET device comprises: an epitaxial wafer comprising a semiconductor substrate and epitaxial layers on a surface of the semiconductor substrate; and a well region, a source region, and a trench gate, which are in the epitaxial layers. The trench gate comprises a gate disposed in a trench at a surface of the epitaxial layers. The source region surrounds the trench. The well region comprises a first layer, a second layer, and a third layer. A bottom of the trench is disposed higher than the first layer and lower than the third layer. The third layer surrounds the trench. Doped region(s) are disposed in the epitaxial layers and beneath the trench, and the first layer surrounds each doped region. A shielding layer is disposed in a part of the epitaxial layers beneath the trench.

公开(公告)号：US20240274657A1

公开(公告)日：2024-08-15

申请号：US18642452

申请日：2024-04-22

Applicant: Huawei Digital Power Technologies Co., Ltd.

Inventor： Kimimori HAMADA ,  Fei HU

IPC: H01L29/06 ,  B60L53/22 ,  H01L21/04 ,  H01L29/16 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/063 ,  H01L21/047 ,  H01L29/0696 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7813 ,  B60L53/22 ,  B60L2210/10 ,  B60L2210/30

Abstract: A semiconductor device includes an N-type semiconductor substrate, a first epitaxial layer, a plurality of gate trenches disposed at intervals, a gate, an interlayer dielectric layer, a source, and a drain. The plurality of gate trenches are disposed at the first epitaxial layer. The gate includes a first gate and a second gate that are in contact with each other. The first gate is filled in the gate trench. The second gate is disposed on top of the first epitaxial layer. The interlayer dielectric layer covers a side that is of the gate and that is away from the semiconductor substrate, and has contact holes that extend in a second direction. The source is disposed on a side that is of the interlayer dielectric layer and that is away from the semiconductor substrate, and is in contact with the first epitaxial layer through the contact hole.

公开(公告)号：US12062691B2

公开(公告)日：2024-08-13

申请号：US18487200

申请日：2023-10-16

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Tatsuo Shimizu

IPC: H01L29/04 ,  B60L53/20 ,  B60R16/023 ,  B61C3/00 ,  B66B11/04 ,  H01L21/225 ,  H01L21/265 ,  H01L21/266 ,  H01L29/16 ,  H01L29/167 ,  H01L29/66 ,  H01L29/78 ,  H02M7/537 ,  H02P27/06

CPC classification number: H01L29/045 ,  B60R16/0231 ,  H01L29/167 ,  H01L29/66068 ,  H01L29/7802 ,  B60L53/20 ,  B61C3/00 ,  B66B11/043 ,  H01L21/2253 ,  H01L21/26513 ,  H01L21/26533 ,  H01L21/266 ,  H01L29/1608 ,  H02M7/537 ,  H02P27/06

Abstract: A semiconductor device of embodiments includes: a silicon carbide layer having a first face and a second face opposite to the first face, and including a p-type silicon carbide region in contact with the first face, a percentage of a first silicon atom among a plurality of silicon atoms present in a first layer as an uppermost layer being equal to or more than 90% and a site position of the first silicon atom being different from a site position of a silicon atom in a third layer from the first face and the same as a site position of a silicon atom in a fifth layer from the first face; a gate electrode; a silicon oxide layer between the silicon carbide layer and the gate electrode; and a region between the silicon carbide layer and the silicon oxide layer including nitrogen.