公开(公告)号：US20210226052A1

公开(公告)日：2021-07-22

申请号：US17202347

申请日：2021-03-16

Applicant: Mitsubishi Electric Corporation

Inventor： Yuichi NAGAHISA ,  Shiro HINO ,  Koji SADAMATSU ,  Hideyuki HATTA ,  Kotaro KAWAHARA

IPC: H01L29/78 ,  H01L29/16 ,  H01L29/417 ,  H01L29/47 ,  H02M7/5387 ,  H01L29/06 ,  H01L21/8234 ,  H01L27/06

Abstract: In an SiC-MOSFET with a built-in Schottky diode, a bipolar current may be passed in a second well region formed at a terminal part to reduce a breakdown voltage. In the SiC-MOSFET with the built-in Schottky diode, a conductive layer in Schottky connection with the second well region is provided on the second well region in the terminal part, and the conductive layer is electrically connected with a source electrode of the MOSFET. A conductive layer contact hole is provided for connecting only the conductive layer and the source electrode.

公开(公告)号：US20170162649A1

公开(公告)日：2017-06-08

申请号：US15439550

申请日：2017-02-22

Applicant: MITSUBISHI ELECTRIC CORPORATION

Inventor： Yasuhiro KAGAWA ,  Akihiko FURUKAWA ,  Shiro HINO ,  Hiroshi WATANABE ,  Masayuki IMAIZUMI

IPC: H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/20 ,  H01L29/78 ,  H01L29/739 ,  H01L29/10 ,  H01L29/16

CPC classification number: H01L29/063 ,  H01L29/0623 ,  H01L29/0696 ,  H01L29/1045 ,  H01L29/105 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/41775 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/66068 ,  H01L29/6631 ,  H01L29/66348 ,  H01L29/66522 ,  H01L29/66666 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7827

Abstract: There is provided a trench-gate type semiconductor device that can prevent breakdown of a gate insulating film caused by a displacement current flowing into a protective diffusion layer at a portion of a trench underlying a gate electrode at a turn-off time and simultaneously improves a current density by narrowing a cell pitch. The semiconductor device has a gate electrode 7 embedded into a trench 5 penetrating a base region 3. The gate electrode 7 is disposed into a lattice shape in a planar view, and a protective diffusion layer 13 is formed in a drift layer 2a at the portion underlying thereof. At least one of blocks divided by the gate electrode 7 is a protective contact region 20 on which the trench 5 is entirely formed. A protective contact 21 for connecting the protective diffusion layer 13 at a bottom portion of the trench 5 and a source electrode 9 is disposed on the protective contact region 20.

公开(公告)号：US20230282741A1

公开(公告)日：2023-09-07

申请号：US18017410

申请日：2020-09-24

Applicant: Mitsubishi Electric Corporation

Inventor： Kotaro KAWAHARA ,  Shiro HINO

IPC: H01L29/78 ,  H01L29/16 ,  H01L29/47

CPC classification number: H01L29/782 ,  H01L29/1608 ,  H01L29/47

Abstract: A silicon carbide semiconductor device includes: a dummy sense region; and a drift layer of a first conductivity type, wherein a MOSFET with a built-in SBD including a first well region of a second conductivity type connected to a source electrode is formed in an active region, a MOSFET with a built-in SBD including a second well region of a second conductivity type connected to a sense pad is formed in an active sense region, and a third well region of a second conductivity type which is not ohmic-connected to any of the source electrode and the sense pad is formed on an upper layer part of the n-type drift layer in the dummy sense region. A gate electrode of the MOSFET with the built-in SBD in the active region and the MOSFET with the built-in SBD in the active sense region is connected to a gate pad.

公开(公告)号：US20220254906A1

公开(公告)日：2022-08-11

申请号：US17625340

申请日：2019-09-06

Applicant: Mitsubishi Electric Corporation

Inventor： Yuichi NAGAHISA ,  Shiro HINO ,  Koji SADAMATSU ,  Kotaro KAWAHARA ,  Hideyuki HATTA ,  Shingo TOMOHISA

IPC: H01L29/739 ,  H01L29/16 ,  H01L29/45 ,  H01L29/872

Abstract: An object of the present invention is to suppress the passage of bipolar current in a silicon carbide semiconductor device by reducing a voltage applied to a terminal well region during reflux operations. An SiC-MOSFET includes a plurality of first well regions, a second well region, a third well region in a surface layer of a drift layer, the first, second, and third well regions being of a second conductivity type. The third well region is provided on the side of the second well region opposite to the first well regions. A unit cell that includes the first well regions includes a unipolar diode. The SiC-MOSFET includes a source electrode connected to the unipolar diode and the ohmic electrode and not having ohmic connection with the second well region and the third well region.

公开(公告)号：US20200295177A1

公开(公告)日：2020-09-17

申请号：US16757767

申请日：2018-12-18

Applicant: Mitsubishi Electric Corporation

Inventor： Shiro HINO ,  Yuichi NAGAHISA ,  Koji SADAMATSU ,  Hideyuki HATTA ,  Kotaro KAWAHARA

IPC: H01L29/78 ,  H01L29/47 ,  H01L29/16 ,  H01L29/06

Abstract: In SiC-MOSFETs including Schottky diodes, passage of a bipolar current to a well region in an edge portion of an active region cannot be sufficiently reduced, which may reduce the reliability of elements. In a SiC-MOSFET including Schottky diodes, the Schottky diodes formed in a terminal region are made higher in density in a plane direction than those formed in the active region or intervals between the Schottky diodes in the plane direction are shortened, without an ohmic connection between the well and the source in the terminal region.

公开(公告)号：US20240355922A1

公开(公告)日：2024-10-24

申请号：US18413662

申请日：2024-01-16

Applicant: Mitsubishi Electric Corporation

Inventor： Katsutoshi SUGAWARA ,  Kotaro KAWAHARA ,  Akifumi IIJIMA ,  Shiro HINO ,  Katsuhiro FUJIYOSHI

IPC: H01L29/78 ,  H01L21/04 ,  H01L29/06 ,  H01L29/08 ,  H01L29/16 ,  H01L29/66 ,  H02P27/08

CPC classification number: H01L29/7806 ,  H01L21/046 ,  H01L29/063 ,  H01L29/086 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7813 ,  H02P27/08

Abstract: A semiconductor device includes: a drift layer of a first conductivity type; well layers of a second conductivity type; a source layer of a first conductivity type; a gate electrode; an interlayer insulating film; and a source electrode, in which a plurality of body diodes constituted by the well layer and the drift layer at positions not overlapping with the gate electrode in plan view include a first operation portion that operates at a first body diode operation voltage and a plurality of second operation portions that operate at a second body diode operation voltage lower than the first body diode operation voltage.

公开(公告)号：US20230139229A1

公开(公告)日：2023-05-04

申请号：US17918116

申请日：2020-05-29

Applicant: Mitsubishi Electric Corporation

Inventor： Kotaro KAWAHARA ,  Shiro HINO

IPC: H01L29/78 ,  H01L29/16

Abstract: A semiconductor device according to the present disclosure includes a sense source electrode provided separately from a source electrode, and diodes. The diodes are provided between the sense source electrode and a drift layer. A turn-on voltage of each diode is lower than an operating voltage of a p-n diode formed of a sense well region and the drift layer or of a dummy sense well region and the drift layer. The diodes allow a current to flow from the sense source electrode toward a drain electrode. The diodes are provided in such a way that they are mixed with facing areas in a dummy sense region in which dummy sense well regions and the diodes are disposed. Each facing area is an area where one of the dummy sense well regions faces one of the gate electrodes via one of the gate insulating films.

公开(公告)号：US20220013663A1

公开(公告)日：2022-01-13

申请号：US17293916

申请日：2018-11-30

Applicant: Mitsubishi Electric Corporation

Inventor： Kotaro KAWAHARA ,  Shiro HINO

IPC: H01L29/78 ,  H01L29/16 ,  H01L29/10

Abstract: A technique for maintaining maximum unipolar current density while improving I2t tolerance is provided. In a semiconductor device, a first impurity layer and a Schottky interface are formed to sandwich a well layer therebetween. A first impurity layer is formed from an outermost layer of the well layer located closer to the Schottky interface than a source layer to below the source layer. The lower face of the first impurity layer is located below the Schottky interface.

公开(公告)号：US20220013438A1

公开(公告)日：2022-01-13

申请号：US17417769

申请日：2019-02-22

Applicant: Mitsubishi Electric Corporation

Inventor： Shiro HINO ,  Junichi NAKASHIMA ,  Takaaki TOMINAGA

IPC: H01L23/482 ,  H02M7/00 ,  H01L29/06 ,  H01L29/16 ,  H01L29/10 ,  H01L29/78 ,  H01L21/04 ,  H01L21/76 ,  H01L21/761 ,  H01L29/66

Abstract: To provide a technique of reducing gate oscillation while suppressing reduction in switching speed. A semiconductor device according to the technique disclosed in the present description includes: a first gate electrode in an active region; a gate pad in a first region different from the active region in a plan view; and a first gate line electrically connecting the first gate electrode and the gate pad to each other. The first gate line is formed into a spiral shape. The first gate line is made of a different type of material from the first gate electrode.

公开(公告)号：US20180323299A1

公开(公告)日：2018-11-08

申请号：US15768251

申请日：2016-09-13

Applicant: Mitsubishi Electric Corporation

Inventor： Takaaki TOMINAGA ,  Shiro HINO

IPC: H01L29/78 ,  H01L29/16 ,  H01L29/10 ,  H01L29/06 ,  H01L29/66 ,  H01L21/04

CPC classification number: H01L29/7802 ,  H01L21/0465 ,  H01L29/06 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0878 ,  H01L29/1037 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7811

Abstract: A silicon carbide semiconductor device includes: a pair of first well regions separated by distance W1 in surface layer portions of a silicon carbide drift layer and having p-type impurity concentration higher than n-type impurity concentration of the silicon carbide drift layer; a pair of second well regions provided adjacent to bottom faces of the first well regions, separated by distance W2 larger than the distance W1 by 0.8 μm or more, and having p-type impurity concentration higher than n-type impurity concentration of the silicon carbide drift layer from 1.1 times to 4.2 times lower than the first well regions; and a highly concentrated JFET region provided between the pair of first well regions and between the pair of second well regions and having n-type impurity concentration higher than that of the silicon carbide drift layer and lower than p-type impurity concentration or the second well regions.