公开(公告)号：US20180191247A1

公开(公告)日：2018-07-05

申请号：US15587742

申请日：2017-05-05

申请人： RICHTEK TECHNOLOGY CORPORATION

发明人： Kuo-Hsuan Lo ,  Tsung-Yi Huang

IPC分类号： H02M3/156 ,  H01L29/739 ,  H01L29/10 ,  H01L29/872

CPC分类号： H01L29/7395 ,  H01L29/0619 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/782 ,  H01L29/7835 ,  H01L29/872

摘要： The invention provides a power device, which includes: an operation layer, including a top surface, a body region and a drift region, the body region and the drift region being connected in a lateral direction, to form a PN junction along a channel width direction between the body region and the drift region; a gate, formed on the top surface, and the PN junction is located under the gate; a source, formed in a portion of the operation layer between the body region and the top surface; a drain, formed in another portion of the operation layer between the drift region and the top surface; a first conduction portion, formed on the top surface for electrically connecting the source; a conduction layer, formed on the first conduction portion and electrically connected to the source via the first conduction portion; and a second conduction portion, formed on the top surface and between the conduction layer and the drift region in a thickness direction, for electrically connecting the drift region and the conduction layer, wherein a Schottky diode is formed by the second conduction portion and the drift region.

公开(公告)号：US09607981B2

公开(公告)日：2017-03-28

申请号：US14827909

申请日：2015-08-17

申请人： FREESCALE SEMICONDUCTOR, INC.

发明人： Weize Chen ,  Hubert M. Bode ,  Richard J. De Souza ,  Patrice M. Parris

IPC分类号： H01L27/06 ,  H01L29/10 ,  H01L27/02 ,  H01L29/06 ,  H01L29/66 ,  H01L29/04 ,  H01L29/16 ,  H01L29/861 ,  H01L29/872 ,  H01L29/78 ,  H01L29/08

CPC分类号： H01L27/0629 ,  H01L27/0288 ,  H01L29/04 ,  H01L29/0646 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/0869 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/16 ,  H01L29/66136 ,  H01L29/66143 ,  H01L29/66681 ,  H01L29/7818 ,  H01L29/782 ,  H01L29/861 ,  H01L29/872

摘要： Embodiments include methods of forming a semiconductor device having a first conductivity type, an isolation structure (including a sinker region and a buried layer), an active device within area of the substrate contained by the isolation structure, and a diode circuit. The buried layer is positioned below the top substrate surface, and has a second conductivity type. The sinker region extends between the top substrate surface and the buried layer, and has the second conductivity type. The active device includes a source region of the first conductivity type, and the diode circuit is connected between the isolation structure and the source region. The diode circuit may include one or more Schottky diodes and/or PN junction diodes. In further embodiments, the diode circuit may include one or more resistive networks in series and/or parallel with the Schottky and/or PN diode(s).

公开(公告)号：US20170069624A1

公开(公告)日：2017-03-09

申请号：US15042473

申请日：2016-02-12

申请人： Kabushiki Kaisha Toshiba

发明人： Keita Takahashi

IPC分类号： H01L27/06 ,  H01L29/78 ,  H01L29/06

CPC分类号： H01L27/0635 ,  H01L27/0629 ,  H01L29/0619 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/732 ,  H01L29/782 ,  H01L29/7835 ,  H01L29/872

摘要： According to one embodiment, the insulating film is provided between the anode region and the cathode region in the surface of the second semiconductor region. The third semiconductor region is provided inside the second semiconductor region. The third semiconductor region covers a corner of the insulating film on the anode region side. The first electrode contacts the anode region and the third semiconductor region. The second electrode contacts the cathode region. The third electrode is provided on the insulating film and positioned on a p-n junction between the second semiconductor region and the third semiconductor region.

摘要翻译： 根据一个实施例，绝缘膜设置在第二半导体区域的表面中的阳极区域和阴极区域之间。 第三半导体区域设置在第二半导体区域内。 第三半导体区域覆盖阳极区域侧的绝缘膜的角部。 第一电极接触阳极区域和第三半导体区域。 第二电极接触阴极区域。 第三电极设置在绝缘膜上并且位于第二半导体区域和第三半导体区域之间的p-n结上。

公开(公告)号：US09490358B2

公开(公告)日：2016-11-08

申请号：US14628987

申请日：2015-02-23

申请人： Semiconductor Components Industries, LLC

发明人： Gary H. Loechelt ,  Gordon M. Grivna

IPC分类号： H01L29/78 ,  H01L29/40 ,  H01L29/66 ,  H01L29/08 ,  H01L29/417 ,  H01L29/423 ,  H01L29/10 ,  H01L29/06 ,  H01L21/28

CPC分类号： H01L29/7809 ,  H01L21/2815 ,  H01L29/063 ,  H01L29/0865 ,  H01L29/0882 ,  H01L29/1095 ,  H01L29/401 ,  H01L29/402 ,  H01L29/41741 ,  H01L29/4175 ,  H01L29/41766 ,  H01L29/42376 ,  H01L29/66674 ,  H01L29/66689 ,  H01L29/66696 ,  H01L29/7816 ,  H01L29/782

摘要： An electronic device can include a buried conductive region and a semiconductor layer over the buried conductive region. The electronic device can further include a horizontally-oriented doped region and a vertical conductive region, wherein the vertical conductive region is electrically connected to the horizontally-oriented doped region and the buried conductive region. The electronic device can still further include an insulating layer overlying the horizontally-oriented doped region, and a first conductive electrode overlying the insulating layer and the horizontally-oriented doped region, wherein a portion of the vertical conductive region does not underlie the first conductive electrode. The electronic device can include a Schottky contact that allows for a Schottky diode to be connected in parallel with a transistor. Processes of forming an electronic device allow a vertical conductive region to be formed after a conductive electrode, a gate electrode, a source region, or both.

摘要翻译： 电子器件可以包括掩埋导电区域和掩埋导电区域上的半导体层。 电子器件还可以包括水平取向的掺杂区域和垂直导电区域，其中垂直导电区域电连接到水平取向掺杂区域和掩埋导电区域。 电子器件还可以进一步包括覆盖水平取向的掺杂区域的绝缘层和覆盖绝缘层和水平取向的掺杂区域的第一导电电极，其中垂直导电区域的一部分不在第一导电电极 。 电子器件可以包括肖特基接触，其允许将肖特基二极管与晶体管并联连接。 形成电子器件的工艺允许在导电电极，栅极电极，源极区域或两者之后形成垂直导电区域。

公开(公告)号：US09356122B2

公开(公告)日：2016-05-31

申请号：US14462548

申请日：2014-08-18

申请人： Alpha & Omega Semiconductor Incorporated

发明人： Mallikarjunaswamy Shekar

IPC分类号： H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L21/768 ,  H01L21/74 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/45 ,  H01L23/495

CPC分类号： H01L29/66681 ,  H01L21/743 ,  H01L21/76879 ,  H01L21/76898 ,  H01L23/49562 ,  H01L23/49575 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/4175 ,  H01L29/41766 ,  H01L29/456 ,  H01L29/66659 ,  H01L29/78 ,  H01L29/782 ,  H01L29/7835 ,  H01L29/7839 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention features methods for forming a field effect transistor on a semiconductor substrate having gate, source and drain regions, with the gate region having a lateral gate channel. A plurality of spaced-apart trenches or through semiconductor vias (TSV) each having an electrically conductive plug formed therein in electrical communication with the gate, source and drain regions are configured to lower the resistance of the bottom source. A contact trench is formed adjacent to the source region and shorts the source region and a body region. A source contact is in electrical communication with the source region; and a drain contact in electrical communication with the drain region, with the source and drain contacts being disposed on opposite sides of the lateral gate channel.

摘要翻译： 本发明的特征在于在具有栅极，源极和漏极区域的半导体衬底上形成场效应晶体管的方法，栅极区域具有横向栅极沟道。 多个间隔开的沟槽或通过半导体通孔（TSV），其各自具有与栅极，源极和漏极区域电连通的形成在其中的导电插塞，被配置为降低底部源的电阻。 形成与源极区域相邻的接触沟槽，并使源极区域和主体区域短路。 源触点与源极区域电连通; 以及与漏极区域电连通的漏极触点，源极和漏极触点设置在横向栅极通道的相对侧上。

公开(公告)号：US09099550B2

公开(公告)日：2015-08-04

申请号：US14528177

申请日：2014-10-30

申请人： RENESAS ELECTRONICS CORPORATION

发明人： Nobuyuki Shirai ,  Nobuyoshi Matsuura ,  Yoshito Nakazawa

IPC分类号： H01L29/76 ,  H01L29/78 ,  H01L29/872 ,  H01L27/06 ,  H01L29/20 ,  H01L29/423 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/40 ,  H01L29/45 ,  H01L29/47

CPC分类号： H01L29/7806 ,  H01L27/0629 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/20 ,  H01L29/402 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/456 ,  H01L29/47 ,  H01L29/475 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/782 ,  H01L29/7823 ,  H01L29/872 ,  H01L29/8725

摘要： A semiconductor device has a MOSFET and a Schottky barrier diode. A source electrode of the MOSFET is disposed over a main surface of the semiconductor substrate and is coupled to a source region in a well region of the semiconductor substrate. The Schottky barrier diode is adjacent to the MOSFET and includes a part of the source electrode and a part of the main surface of the semiconductor substrate.

摘要翻译： 半导体器件具有MOSFET和肖特基势垒二极管。 MOSFET的源极设置在半导体衬底的主表面上，并且耦合到半导体衬底的阱区中的源极区。 肖特基势垒二极管与MOSFET相邻，并且包括源电极的一部分和半导体衬底的主表面的一部分。

公开(公告)号：US09054174B2

公开(公告)日：2015-06-09

申请号：US13913021

申请日：2013-06-07

申请人： Hitachi, Ltd.

发明人： Digh Hisamoto ,  Naoki Tega ,  Kumiko Konishi ,  Hiroyuki Matsushima

IPC分类号： H01L29/12 ,  H01L29/78 ,  H01L29/66 ,  H01L29/739 ,  H01L29/16 ,  H01L29/872 ,  H01L21/04 ,  H01L29/417 ,  H01L29/47 ,  H01L29/49 ,  H01L29/51 ,  H01L29/06

CPC分类号： H01L29/78 ,  H01L21/0495 ,  H01L29/0619 ,  H01L29/1608 ,  H01L29/41766 ,  H01L29/41775 ,  H01L29/47 ,  H01L29/495 ,  H01L29/517 ,  H01L29/66068 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/7395 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/782 ,  H01L29/7839 ,  H01L29/872

摘要： In a MOSFET using a SiC substrate, a source region having low resistance and high injection efficiency is formed without performing a high-temperature heat treatment.A vertical Schottky barrier transistor in which a source region SR on a SiC epitaxial substrate is constituted by a metal material is formed. The source region SR composed of a metal material can be brought into a low resistance state without performing a high-temperature activation treatment. Further, by segregating a conductive impurity DP at an interface between the source region SR composed of a metal material and the SiC epitaxial substrate, the Schottky barrier height can be reduced, and the carrier injection efficiency from the source region SR can be improved.

摘要翻译： 在使用SiC衬底的MOSFET中，形成具有低电阻和高注入效率的源区，而不进行高温热处理。 形成其中SiC外延基板上的源极区域SR由金属材料构成的垂直肖特基势垒晶体管。 由金属材料构成的源区SR可以进行低电阻状态而不进行高温活化处理。 此外，通过在由金属材料构成的源极区域SR与SiC外延基板之间的界面处分离导电性杂质DP，可以降低肖特基势垒高度，能够提高源极区域SR的载流子注入效率。

公开(公告)号：US20150084062A1

公开(公告)日：2015-03-26

申请号：US14255405

申请日：2014-04-17

申请人： Cree, Inc.

发明人： Vipindas Pala ,  Lin Cheng ,  Anant Kumar Agarwal ,  John Williams Palmour ,  Edward Robert Van Brunt

IPC分类号： H01L29/10 ,  H01L29/66 ,  H01L21/265 ,  H01L29/78

CPC分类号： H01L29/7806 ,  H01L21/046 ,  H01L21/26506 ,  H01L29/0619 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/36 ,  H01L29/47 ,  H01L29/66068 ,  H01L29/66734 ,  H01L29/7813 ,  H01L29/782 ,  H01L29/7828 ,  H01L29/8611 ,  H01L29/872

摘要： A vertical field-effect transistor (FET) device includes a monolithically integrated bypass diode connected between a source contact and a drain contact of the vertical FET device. According to one embodiment, the vertical FET device includes a pair of junction implants separated by a junction field-effect transistor (JFET) region. At least one of the junction implants of the vertical FET device includes a deep well region that is shared with the integrated bypass diode, such that the shared deep well region functions as both a source junction in the vertical FET device and a junction barrier region in the integrated bypass diode. The vertical FET device and the integrated bypass diode may include a substrate, a drift layer over the substrate, and a spreading layer over the drift layer, such that the junction implants of the vertical FET device are formed in the spreading layer.

公开(公告)号：US20130341705A1

公开(公告)日：2013-12-26

申请号：US14015029

申请日：2013-08-30

申请人： Texas Instruments Incorporated

发明人： Venkat Raghavan ,  Andrew D. Strachan

IPC分类号： H01L27/06 ,  H01L29/66

CPC分类号： H01L27/06 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/41758 ,  H01L29/47 ,  H01L29/66143 ,  H01L29/782

摘要： In an LDMOS device leakage and forward conduction parameters are adjusted by integrating an Schottky diode into the LDMOS by substituting one or more n+ source regions with Schottky diodes.

摘要翻译： 在LDMOS器件中，通过用肖特基二极管代替一个或多个n +源极区，将肖特基二极管集成到LDMOS中来调节泄漏和正向传导参数。

公开(公告)号：US20130328062A1

公开(公告)日：2013-12-12

申请号：US13913021

申请日：2013-06-07

申请人： Hitachi, Ltd.

发明人： Digh Hisamoto ,  Naoki Tega ,  Kumiko Konishi ,  Hiroyuki Matsushima

IPC分类号： H01L29/78 ,  H01L29/16 ,  H01L29/66

CPC分类号： H01L29/78 ,  H01L21/0495 ,  H01L29/0619 ,  H01L29/1608 ,  H01L29/41766 ,  H01L29/41775 ,  H01L29/47 ,  H01L29/495 ,  H01L29/517 ,  H01L29/66068 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/7395 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/782 ,  H01L29/7839 ,  H01L29/872

摘要： In a MOSFET using a SiC substrate, a source region having low resistance and high injection efficiency is formed without performing a high-temperature heat treatment.A vertical Schottky barrier transistor in which a source region SR on a SiC epitaxial substrate is constituted by a metal material is formed. The source region SR composed of a metal material can be brought into a low resistance state without performing a high-temperature activation treatment. Further, by segregating a conductive impurity DP at an interface between the source region SR composed of a metal material and the SiC epitaxial substrate, the Schottky barrier height can be reduced, and the carrier injection efficiency from the source region SR can be improved.

摘要翻译： 在使用SiC衬底的MOSFET中，形成具有低电阻和高注入效率的源区，而不进行高温热处理。 形成其中SiC外延基板上的源极区域SR由金属材料构成的垂直肖特基势垒晶体管。 由金属材料构成的源区SR可以进行低电阻状态而不进行高温活化处理。 此外，通过在由金属材料构成的源极区域SR与SiC外延基板之间的界面处分离导电性杂质DP，可以降低肖特基势垒高度，能够提高源极区域SR的载流子注入效率。