公开(公告)号：US09449904B2

公开(公告)日：2016-09-20

申请号：US14514254

申请日：2014-10-14

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Nobuyuki Shirai ,  Nobuyoshi Matsuura

IPC: H01L23/498 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L21/56 ,  H01L29/06 ,  H01L29/417 ,  H01L29/45 ,  H01L29/49 ,  H01L23/00 ,  H01L23/495

CPC classification number: H01L23/49811 ,  H01L21/565 ,  H01L23/49513 ,  H01L23/4952 ,  H01L23/49541 ,  H01L23/49562 ,  H01L24/05 ,  H01L24/13 ,  H01L29/0615 ,  H01L29/41766 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/4941 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/78 ,  H01L29/7811 ,  H01L29/7813 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/05008 ,  H01L2224/05023 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05568 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/06181 ,  H01L2224/1131 ,  H01L2224/13021 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/14151 ,  H01L2224/16 ,  H01L2224/16245 ,  H01L2224/29139 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2924/0102 ,  H01L2924/01079 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/01029

Abstract: A semiconductor device includes a gate electrode GE electrically connected to a gate portion which is made of a polysilicon film provided in the inside of a plurality of grooves formed in a striped form along the direction of T of a chip region CA wherein the gate electrode GE is formed as a film at the same layer level as a source electrode SE electrically connected to a source region formed between adjacent stripe-shaped grooves and the gate electrode GE is constituted of a gate electrode portion G1 formed along a periphery of the chip region CA and a gate finger portion G2 arranged so that the chip region CA is divided into halves along the direction of X. The source electrode SE is constituted of an upper portion and a lower portion, both relative to the gate finger portion G2, and the gate electrode GE and the source electrode SE are connected to a lead frame via a bump electrode.

公开(公告)号：US09099550B2

公开(公告)日：2015-08-04

申请号：US14528177

申请日：2014-10-30

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Nobuyuki Shirai ,  Nobuyoshi Matsuura ,  Yoshito Nakazawa

IPC: H01L29/76 ,  H01L29/78 ,  H01L29/872 ,  H01L27/06 ,  H01L29/20 ,  H01L29/423 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/40 ,  H01L29/45 ,  H01L29/47

CPC classification number: H01L29/7806 ,  H01L27/0629 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/20 ,  H01L29/402 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/456 ,  H01L29/47 ,  H01L29/475 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/782 ,  H01L29/7823 ,  H01L29/872 ,  H01L29/8725

Abstract: A semiconductor device has a MOSFET and a Schottky barrier diode. A source electrode of the MOSFET is disposed over a main surface of the semiconductor substrate and is coupled to a source region in a well region of the semiconductor substrate. The Schottky barrier diode is adjacent to the MOSFET and includes a part of the source electrode and a part of the main surface of the semiconductor substrate.

Abstract translation: 半导体器件具有MOSFET和肖特基势垒二极管。 MOSFET的源极设置在半导体衬底的主表面上，并且耦合到半导体衬底的阱区中的源极区。 肖特基势垒二极管与MOSFET相邻，并且包括源电极的一部分和半导体衬底的主表面的一部分。

公开(公告)号：US08928071B2

公开(公告)日：2015-01-06

申请号：US13844950

申请日：2013-03-16

Applicant: Renesas Electronics Corporation

Inventor： Nobuyuki Shirai ,  Nobuyoshi Matsuura ,  Yoshito Nakazawa

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/872 ,  H01L29/45 ,  H01L29/10 ,  H01L29/06 ,  H01L29/40 ,  H01L29/08 ,  H01L29/47

CPC classification number: H01L29/7806 ,  H01L27/0629 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/20 ,  H01L29/402 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/456 ,  H01L29/47 ,  H01L29/475 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/782 ,  H01L29/7823 ,  H01L29/872 ,  H01L29/8725

Abstract: A semiconductor device has a semiconductor substrate with a plurality of transistor cell regions. Each transistor cell region includes a plurality of trenches disposed in the semiconductor substrate, a well region between the plurality of trenches, and a source region of a MOSFET in the well region. A source electrode of the MOSFET is in contact with a top surface of the source region in each of the plurality of transistor cell regions. The source electrode is in contact with a part of a main surface of the semiconductor substrate so as to form a Schottky junction in a Schottky cell region disposed between the plurality of transistor cell regions. The Schottky junction is lower than a portion of the main surface between the Schottky junction and one of the transistor cell regions.

Abstract translation: 半导体器件具有具有多个晶体管单元区域的半导体衬底。 每个晶体管单元区域包括设置在半导体衬底中的多个沟槽，多个沟槽之间的阱区域和阱区域中的MOSFET的源极区域。 MOSFET的源电极与多个晶体管单元区域中的每一个中的源极区域的顶表面接触。 源电极与半导体衬底的主表面的一部分接触，以便在设置在多个晶体管单元区域之间的肖特基电池区域中形成肖特基结。 肖特基结低于肖特基结和一个晶体管单元区之间的主表面的一部分。

公开(公告)号：US10074744B2

公开(公告)日：2018-09-11

申请号：US15625771

申请日：2017-06-16

Applicant: Renesas Electronics Corporation

Inventor： Hideo Numabe ,  Nobuyuki Shirai ,  Hirokazu Kato ,  Tomoaki Uno ,  Kazuyuki Umezu

IPC: H01L29/78 ,  H01L29/40 ,  H01L29/423 ,  H01L29/08 ,  H01L29/06 ,  H01L29/417 ,  H01L29/10 ,  H01L23/535

CPC classification number: H01L29/7813 ,  H01L23/535 ,  H01L24/05 ,  H01L24/06 ,  H01L24/29 ,  H01L24/37 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/84 ,  H01L29/0696 ,  H01L29/0865 ,  H01L29/0882 ,  H01L29/1033 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/4236 ,  H01L2224/04026 ,  H01L2224/04034 ,  H01L2224/04042 ,  H01L2224/05082 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05644 ,  H01L2224/0603 ,  H01L2224/29101 ,  H01L2224/29339 ,  H01L2224/32245 ,  H01L2224/37011 ,  H01L2224/371 ,  H01L2224/37124 ,  H01L2224/37147 ,  H01L2224/40245 ,  H01L2224/45144 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/73221 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2224/32225

Abstract: A control electrode GE1 is formed in a lower portion of a trench TR1 formed in a semiconductor substrate SUB, and a gate electrode GE2 is formed in an upper portion inside the trench TR1. An insulating film G1 is formed between the control electrode GE1 and a side wall and a bottom surface of the trench TR1, an insulating film G2 is formed between the side wall of the trench TR1 and the gate electrode GE2, and an insulating film G3 is formed between the control electrode GE1 and the gate electrode GE2. A region adjacent to the trench TR1 includes an n+-type semiconductor region NR for a source, a p-type semiconductor region PR for a channel formation, and a semiconductor region for a drain. A wiring connected to the control electrode GE1 is not connected to a wiring connected to the gate electrode GE2, and is not connected to a wiring connected to the n+-type semiconductor region NR for a source.

公开(公告)号：US20170288053A1

公开(公告)日：2017-10-05

申请号：US15625771

申请日：2017-06-16

Applicant: Renesas Electronics Corporation

Inventor： Hideo Numabe ,  Nobuyuki Shirai ,  Hirokazu Kato ,  Tomoaki Uno ,  Kazuyuki Umezu

IPC: H01L29/78 ,  H01L29/40 ,  H01L29/423 ,  H01L29/08 ,  H01L29/06 ,  H01L23/535 ,  H01L29/417 ,  H01L29/10

CPC classification number: H01L29/7813 ,  H01L23/535 ,  H01L29/0696 ,  H01L29/0865 ,  H01L29/0882 ,  H01L29/1033 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/4236 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/371 ,  H01L2224/37124 ,  H01L2224/37147 ,  H01L2224/40245 ,  H01L2224/45144 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A control electrode GE1 is formed in a lower portion of a trench TR1 formed in a semiconductor substrate SUB, and a gate electrode GE2 is formed in an upper portion inside the trench TR1. An insulating film G1 is formed between the control electrode GE1 and a side wall and a bottom surface of the trench TR1, an insulating film G2 is formed between the side wall of the trench TR1 and the gate electrode GE2, and an insulating film G3 is formed between the control electrode GE1 and the gate electrode GE2. A region adjacent to the trench TR1 includes an n+-type semiconductor region NR for a source, a p-type semiconductor region PR for a channel formation, and a semiconductor region for a drain. A wiring connected to the control electrode GE1 is not connected to a wiring connected to the gate electrode GE2, and is not connected to a wiring connected to the n+-type semiconductor region NR for a source.

公开(公告)号：US09711637B2

公开(公告)日：2017-07-18

申请号：US14406991

申请日：2014-01-31

Applicant: Renesas Electronics Corporation

Inventor： Hideo Numabe ,  Nobuyuki Shirai ,  Hirokazu Kato ,  Tomoaki Uno ,  Kazuyuki Umezu

IPC: H01L29/78 ,  H01L29/40 ,  H01L29/06 ,  H01L29/10 ,  H01L23/535 ,  H01L29/08 ,  H01L29/417 ,  H01L29/423

CPC classification number: H01L29/7813 ,  H01L23/535 ,  H01L29/0696 ,  H01L29/0865 ,  H01L29/0882 ,  H01L29/1033 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/4236 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/371 ,  H01L2224/37124 ,  H01L2224/37147 ,  H01L2224/40245 ,  H01L2224/45144 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A control electrode GE1 is formed in a lower portion of a trench TR1 formed in a semiconductor substrate SUB, and a gate electrode GE2 is formed in an upper portion inside the trench TR1. An insulating film G1 is formed between the control electrode GE1 and a side wall and a bottom surface of the trench TR1, an insulating film G2 is formed between the side wall of the trench TR1 and the gate electrode GE2, and an insulating film G3 is formed between the control electrode GE1 and the gate electrode GE2. A region adjacent to the trench TR1 includes an n+-type semiconductor region NR for a source, a p-type semiconductor region PR for a channel formation, and a semiconductor region for a drain. A wiring connected to the control electrode GE1 is not connected to a wiring connected to the gate electrode GE2, and is not connected to a wiring connected to the n+-type semiconductor region NR for a source.

公开(公告)号：US20150028400A1

公开(公告)日：2015-01-29

申请号：US14514254

申请日：2014-10-14

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Nobuyuki Shirai ,  Nobuyoshi Matsuura

IPC: H01L23/498 ,  H01L29/78

CPC classification number: H01L23/49811 ,  H01L21/565 ,  H01L23/49513 ,  H01L23/4952 ,  H01L23/49541 ,  H01L23/49562 ,  H01L24/05 ,  H01L24/13 ,  H01L29/0615 ,  H01L29/41766 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/4941 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/78 ,  H01L29/7811 ,  H01L29/7813 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/05008 ,  H01L2224/05023 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05568 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/06181 ,  H01L2224/1131 ,  H01L2224/13021 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/14151 ,  H01L2224/16 ,  H01L2224/16245 ,  H01L2224/29139 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2924/0102 ,  H01L2924/01079 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/01029

Abstract: A semiconductor device includes a gate electrode GE electrically connected to a gate portion which is made of a polysilicon film provided in the inside of a plurality of grooves formed in a striped form along the direction of T of a chip region CA wherein the gate electrode GE is formed as a film at the same layer level as a source electrode SE electrically connected to a source region formed between adjacent stripe-shaped grooves and the gate electrode GE is constituted of a gate electrode portion G1 formed along a periphery of the chip region CA and a gate finger portion G2 arranged so that the chip region CA is divided into halves along the direction of X. The source electrode SE is constituted of an upper portion and a lower portion, both relative to the gate finger portion G2, and the gate electrode GE and the source electrode SE are connected to a lead frame via a bump electrode.

Abstract translation: 半导体器件包括栅极电极GE，栅极电极GE电连接到栅极部分，栅极部分由沿芯片区域CA的T的方向形成的多个沟槽的内部设置的多晶硅膜制成，其中栅电极GE 形成为与与形成在相邻条形槽之间的源极区域电连接的源极电极SE相同的层级，并且栅电极GE由沿着芯片区域CA的周边形成的栅电极部分G1 以及栅极指部分G2，其布置成使得芯片区域CA沿着X方向被分成两半。源电极SE由相对于栅极指部分G2的两个上部和下部构成，并且栅极 电极GE和源电极SE通过凸块电极连接到引线框架。