公开(公告)号：US12090579B2

公开(公告)日：2024-09-17

申请号：US17856765

申请日：2022-07-01

Applicant: INDIUM CORPORATION

Inventor： Weiping Liu ,  Ning-Cheng Lee

IPC: C22C13/00 ,  B23K35/26 ,  C22C13/02 ,  H01L23/00

CPC classification number: B23K35/262 ,  C22C13/00 ,  C22C13/02 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/81 ,  H01L2224/04026 ,  H01L2224/05082 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05639 ,  H01L2224/1131 ,  H01L2224/13111 ,  H01L2224/16225 ,  H01L2224/29111 ,  H01L2224/32245 ,  H01L2224/81815 ,  H01L2224/83815 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01083 ,  H01L2924/014 ,  H01L2224/05639 ,  H01L2924/00014 ,  H01L2224/05166 ,  H01L2924/00014 ,  H01L2224/05155 ,  H01L2924/00014 ,  H01L2224/29111 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/01051 ,  H01L2924/014 ,  H01L2224/13111 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/01051 ,  H01L2924/014 ,  H01L2224/29111 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/01051 ,  H01L2924/01049 ,  H01L2924/01083 ,  H01L2924/014 ,  H01L2224/13111 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/01051 ,  H01L2924/01049 ,  H01L2924/01083 ,  H01L2924/014

Abstract: A SnAgCuSbBi-based Pb-free solder alloy is disclosed. The disclosed solder alloy is particularly suitable for, but not limited to, producing solder joints, in the form of solder preforms, solder balls, solder powder, or solder paste (a mixture of solder powder and flux), for harsh environment electronics.

公开(公告)号：US20230178506A1

公开(公告)日：2023-06-08

申请号：US17917270

申请日：2020-06-05

Applicant: Mitsubishi Electric Corporation

Inventor： Tatsushi MORISADA

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/498 ,  H01L23/31

CPC classification number: H01L24/13 ,  H01L21/565 ,  H01L23/3121 ,  H01L23/49811 ,  H01L24/05 ,  H01L24/08 ,  H01L24/11 ,  H01L24/16 ,  H01L24/06 ,  H01L24/32 ,  H01L2224/0603 ,  H01L2224/1131 ,  H01L2224/1369 ,  H01L2224/1624 ,  H01L2224/05547 ,  H01L2224/05568 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/06181 ,  H01L2224/08225 ,  H01L2224/11332 ,  H01L2224/11334 ,  H01L2224/11848 ,  H01L2224/11849 ,  H01L2224/13017 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13551 ,  H01L2224/13566 ,  H01L2224/13639 ,  H01L2224/13647 ,  H01L2224/13655 ,  H01L2224/32245

Abstract: A power semiconductor apparatus includes a conductive circuit pattern, a power semiconductor device, a sealing member, a conductive post, and a conductive post. A first conductive post is connected to the conductive circuit pattern. A second conductive post is connected to the power semiconductor device. The first conductive post includes a metal pin and a conductive bonding member. The conductive post includes a metal pin and a conductive bonding member.

公开(公告)号：US20180076162A1

公开(公告)日：2018-03-15

申请号：US15804478

申请日：2017-11-06

Applicant: International Business Machines Corporation

Inventor： Akihiro HORIBE ,  Keiji MATSUMOTO ,  Keishi OKAMOTO ,  Kazushige TORIYAMA

IPC: H01L23/00 ,  H01L25/00 ,  B23K3/06 ,  H01L23/522 ,  H01L23/498 ,  H01L23/34 ,  H01L21/768 ,  H01L21/48 ,  H01L25/065 ,  H01L23/488 ,  H01L23/48

CPC classification number: H01L24/13 ,  B23K3/0623 ,  H01L21/4867 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/34 ,  H01L23/345 ,  H01L23/481 ,  H01L23/488 ,  H01L23/49816 ,  H01L23/49894 ,  H01L23/5226 ,  H01L24/08 ,  H01L24/11 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/742 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05027 ,  H01L2224/11013 ,  H01L2224/1131 ,  H01L2224/11312 ,  H01L2224/11416 ,  H01L2224/1148 ,  H01L2224/11618 ,  H01L2224/13013 ,  H01L2224/13014 ,  H01L2224/13015 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/14051 ,  H01L2224/16111 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/17519 ,  H01L2224/27 ,  H01L2224/27416 ,  H01L2224/27515 ,  H01L2224/27618 ,  H01L2224/29011 ,  H01L2224/29012 ,  H01L2224/29076 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/81 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81204 ,  H01L2224/81801 ,  H01L2224/81815 ,  H01L2224/83 ,  H01L2224/83203 ,  H01L2224/83204 ,  H01L2224/9211 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06568 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/06 ,  H01L2924/12042 ,  H01L2924/3512 ,  H01L2924/37001 ,  H01L2924/3841 ,  H01L2224/11 ,  H01L2924/00014 ,  H01L2924/0103 ,  H01L2924/01083 ,  H01L2924/01049 ,  H01L2924/01051 ,  H01L2924/01028 ,  H01L2924/01027 ,  H01L2924/01032 ,  H01L2924/01026 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/00013 ,  H01L2924/00012

Abstract: Highly reliable chip mounting is accomplished by using a substrate having such a shape that a stress exerted on a flip-chip-connected chip can be reduced, so that the stress exerted on the chip is reduced and separation of an interlayer insulating layer having a low dielectric constant (low-k) is minimized. Specifically, in a chip mounting structure, a chip including an interlayer insulating layer having a low dielectric constant (low-k) is flip-chip connected to a substrate via bumps is shown. In the chip mounting structure, the substrate has such a shape that a mechanical stress exerted on the interlayer insulating layer at corner portions of the chip due to a thermal stress is reduced, the thermal stress occurring due to a difference in coefficient of thermal expansion between the chip and the substrate.

公开(公告)号：US09847310B2

公开(公告)日：2017-12-19

申请号：US14812861

申请日：2015-07-29

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Michael J. Seddon ,  Francis J. Carney

IPC: H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L23/498

CPC classification number: H01L24/17 ,  H01L23/49811 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/03828 ,  H01L2224/0401 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05639 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1131 ,  H01L2224/11334 ,  H01L2224/11849 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13155 ,  H01L2224/13166 ,  H01L2224/13294 ,  H01L2224/13311 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/16245 ,  H01L2224/16503 ,  H01L2224/81024 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81211 ,  H01L2224/81411 ,  H01L2224/81439 ,  H01L2224/81447 ,  H01L2224/8181 ,  H01L2224/81815 ,  H01L2224/81825 ,  H01L2224/97 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/15738 ,  H01L2924/15747 ,  H01L2924/3841 ,  H01L2924/00014 ,  H01L2224/81

Abstract: A method of bonding a plurality of die having first and second metal layers on a die surface to a board, comprising placing a first die onto a board comprising one of a ceramic or substrate board or metal lead frame having a solderable surface and placing the first die and the board into a reflow oven. The method includes reflowing at a first reflow temperature for a first period until the first metal board layer and at least one of the first and second metal die layers of the first die form an alloy to adhere the first die to the board. The newly formed alloy has a higher melting temperature than the first reflow temperature. Accordingly, additional die may be reflowed and attached to the board without causing the bonding of the first die to the board to fail if the same reflow temperature is used.

公开(公告)号：US20170271242A1

公开(公告)日：2017-09-21

申请号：US15614339

申请日：2017-06-05

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hsiao Yun Lo ,  Yung-Chi Lin ,  Yang-Chih Hsueh ,  Tsang-Jiuh Wu ,  Wen-Chih Chiou

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/00 ,  H01L23/532 ,  H01L21/288 ,  H01L23/525

CPC classification number: H01L23/481 ,  H01L21/2885 ,  H01L21/76847 ,  H01L21/7685 ,  H01L21/76885 ,  H01L21/76898 ,  H01L23/525 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/53242 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L29/43 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/0347 ,  H01L2224/03616 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05005 ,  H01L2224/05018 ,  H01L2224/05023 ,  H01L2224/05025 ,  H01L2224/05026 ,  H01L2224/05099 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05157 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/0518 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05541 ,  H01L2224/05552 ,  H01L2224/05567 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/0558 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/0568 ,  H01L2224/05681 ,  H01L2224/1131 ,  H01L2224/1134 ,  H01L2224/11849 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2924/00 ,  H01L2924/00011 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/207

Abstract: An interconnection structure and method disclosed for providing an interconnection structure that includes conductive features having reduced topographic variations. The interconnection structure includes a contact pad disposed over a substrate. The contact pad includes a first layer of a first conductive material and a second layer of a second conductive material over the first layer. The first conductive material and the second conductive material are made of substantially the same material and have a first average grain size and a second average grain size that is smaller than the first average grain size. The interconnection structure also includes a passivation layer covering the substrate and the contact pad, and the passivation layer has an opening exposing the contact pad.

公开(公告)号：US09673132B2

公开(公告)日：2017-06-06

申请号：US14511006

申请日：2014-10-09

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hsiao Yun Lo ,  Yung-Chi Lin ,  Yang-Chih Hsueh ,  Tsang-Jiuh Wu ,  Wen-Chih Chiou

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/00 ,  H01L23/532 ,  H01L21/288 ,  H01L23/525

CPC classification number: H01L23/481 ,  H01L21/2885 ,  H01L21/7685 ,  H01L21/76885 ,  H01L21/76898 ,  H01L23/525 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/53242 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/0347 ,  H01L2224/03616 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05005 ,  H01L2224/05018 ,  H01L2224/05023 ,  H01L2224/05025 ,  H01L2224/05026 ,  H01L2224/05099 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05157 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/0518 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05541 ,  H01L2224/05567 ,  H01L2224/05568 ,  H01L2224/05571 ,  H01L2224/0558 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/0568 ,  H01L2224/05681 ,  H01L2224/05684 ,  H01L2224/1131 ,  H01L2224/1134 ,  H01L2224/11849 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/00012 ,  H01L2924/207 ,  H01L2224/05552 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2224/81805

Abstract: An interconnection structure and method disclosed for providing an interconnection structure that includes conductive features having reduced topographic variations. The interconnection structure includes a contact pad disposed over a substrate. The contact pad includes a first layer of a first conductive material and a second layer of a second conductive material over the first layer. The first conductive material and the second conductive material are made of substantially the same material and have a first average grain size and a second average grain size that is smaller than the first average grain size. The interconnection structure also includes a passivation layer covering the substrate and the contact pad, and the passivation layer has an opening exposing the contact pad.

公开(公告)号：US09570414B2

公开(公告)日：2017-02-14

申请号：US14474686

申请日：2014-09-02

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Satoshi Tsukiyama ,  Masatoshi Fukuda ,  Yukifumi Oyama ,  Shinya Fukayama

IPC: H01L21/00 ,  H01L23/00 ,  H01L25/00 ,  H01L25/07 ,  H01L23/544 ,  H01L21/56

CPC classification number: H01L24/81 ,  H01L21/563 ,  H01L23/544 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/17 ,  H01L25/074 ,  H01L25/50 ,  H01L2223/54426 ,  H01L2223/54473 ,  H01L2224/10135 ,  H01L2224/1131 ,  H01L2224/11334 ,  H01L2224/13014 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/1319 ,  H01L2224/1403 ,  H01L2224/1415 ,  H01L2224/14505 ,  H01L2224/16146 ,  H01L2224/1705 ,  H01L2224/17517 ,  H01L2224/73204 ,  H01L2224/8113 ,  H01L2224/81139 ,  H01L2224/81193 ,  H01L2224/81194 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/81862 ,  H01L2224/81907 ,  H01L2224/83104 ,  H01L2224/92125 ,  H01L2924/35 ,  H01L2924/01083 ,  H01L2924/01049 ,  H01L2924/00014 ,  H01L2224/8185 ,  H01L2924/0665 ,  H01L2924/01047 ,  H01L2924/01029

Abstract: According to one embodiment, a first electrode is formed on a first face of a first semiconductor chip, and a second electrode and a protrusion are formed on a second face of a second semiconductor chip. The first semiconductor chip and the second semiconductor chip are spaced from one another by the protrusion in such a manner that the first face and the second face face each other. The first semiconductor chip and the second semiconductor chip are subject to reflow to be electrically connected to each other, and then the protrusion is cured at a temperature lower than a reflow temperature.

Abstract translation: 根据一个实施例，第一电极形成在第一半导体芯片的第一面上，第二电极和突起形成在第二半导体芯片的第二面上。 第一半导体芯片和第二半导体芯片通过突起彼此间隔开，使得第一面和第二面彼此面对。 第一半导体芯片和第二半导体芯片经受回流以彼此电连接，然后突起在低于回流温度的温度下固化。

公开(公告)号：US20170033067A1

公开(公告)日：2017-02-02

申请号：US14809296

申请日：2015-07-27

Applicant: Infineon Technologies AG

Inventor： Stefan Kramp

IPC: H01L23/00 ,  H01L21/768

CPC classification number: H01L24/06 ,  H01L21/76832 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/27 ,  H01L24/29 ,  H01L24/45 ,  H01L24/73 ,  H01L2224/0345 ,  H01L2224/03614 ,  H01L2224/0381 ,  H01L2224/03901 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05022 ,  H01L2224/05023 ,  H01L2224/05124 ,  H01L2224/05166 ,  H01L2224/05568 ,  H01L2224/05572 ,  H01L2224/05583 ,  H01L2224/05611 ,  H01L2224/05647 ,  H01L2224/0603 ,  H01L2224/06505 ,  H01L2224/1131 ,  H01L2224/11332 ,  H01L2224/11849 ,  H01L2224/13023 ,  H01L2224/13118 ,  H01L2224/13123 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/16245 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45157 ,  H01L2224/48245 ,  H01L2224/48491 ,  H01L2224/73207 ,  H01L2224/8181 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/0105 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/0361 ,  H01L2924/01074

Abstract: According to various embodiments, a semiconductor device may include: at least one first contact pad on a front side of the semiconductor device; at least one second contact pad on the front side of the semiconductor device; a layer stack disposed at least partially over the at least one first contact pad, wherein the at least one second contact pad is at least partially free of the layer stack; wherein the layer stack includes at least an adhesion layer and a metallization layer; and wherein the metallization layer includes a metal alloy and wherein the adhesion layer is disposed between the metallization layer and the at least one first contact pad for adhering the metal alloy of the metallization layer to the at least one first contact pad.

Abstract translation: 根据各种实施例，半导体器件可以包括：在半导体器件的正面上的至少一个第一接触焊盘; 在所述半导体器件的正面上的至少一个第二接触焊盘; 至少部分地布置在所述至少一个第一接触垫上的层堆叠，其中所述至少一个第二接触焊盘至少部分地不含所述层堆叠; 其中所述层堆叠至少包括粘附层和金属化层; 并且其中所述金属化层包括金属合金，并且其中所述粘合层设置在所述金属化层和所述至少一个第一接触焊盘之间，用于将所述金属化层的所述金属合金粘附到所述至少一个第一接触焊盘。

公开(公告)号：US20170028477A1

公开(公告)日：2017-02-02

申请号：US15302712

申请日：2015-04-10

Applicant: Alpha Metals, Inc.

Inventor： Rohan P. Setna ,  Nirmalya Kumar Chaki ,  Poulami Sengupta Roy ,  Siuli Sarkar ,  Sutapa Mukherjee

IPC: B22F9/24 ,  B22F1/02 ,  B22F9/04 ,  H01L23/00 ,  C09J9/02 ,  C09J11/04 ,  C09C1/62 ,  B22F1/00 ,  C09J1/00

CPC classification number: B22F9/24 ,  B22F1/0014 ,  B22F1/0074 ,  B22F1/025 ,  B22F9/04 ,  B22F2009/043 ,  B22F2301/10 ,  B22F2301/255 ,  C01P2004/20 ,  C01P2004/32 ,  C01P2004/51 ,  C01P2004/61 ,  C01P2006/11 ,  C01P2006/12 ,  C01P2006/80 ,  C09C1/62 ,  C09C1/622 ,  C09C1/627 ,  C09J1/00 ,  C09J9/02 ,  C09J11/04 ,  H01L24/27 ,  H01L24/29 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/111 ,  H01L2224/1111 ,  H01L2224/1131 ,  H01L2224/11312 ,  H01L2224/1132 ,  H01L2224/11438 ,  H01L2224/1144 ,  H01L2224/11505 ,  H01L2224/13294 ,  H01L2224/13339 ,  H01L2224/13344 ,  H01L2224/13347 ,  H01L2224/13355 ,  H01L2224/13387 ,  H01L2224/1339 ,  H01L2224/13439 ,  H01L2224/1349 ,  H01L2224/13499 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/271 ,  H01L2224/2711 ,  H01L2224/2731 ,  H01L2224/27312 ,  H01L2224/2732 ,  H01L2224/27438 ,  H01L2224/2744 ,  H01L2224/27505 ,  H01L2224/29011 ,  H01L2224/29139 ,  H01L2224/29147 ,  H01L2224/29294 ,  H01L2224/29339 ,  H01L2224/29344 ,  H01L2224/29347 ,  H01L2224/29355 ,  H01L2224/29387 ,  H01L2224/2939 ,  H01L2224/29439 ,  H01L2224/2949 ,  H01L2224/29499 ,  H01L2224/32145 ,  H01L2224/32227 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81203 ,  H01L2224/8121 ,  H01L2224/8184 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83203 ,  H01L2224/8321 ,  H01L2224/8384 ,  H01L2224/94 ,  H01L2924/12041 ,  H01L2924/00014 ,  H01L2924/0105 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/01028 ,  H01L2924/0103 ,  H01L2924/0503 ,  H01L2924/01005 ,  H01L2924/00012 ,  H01L2224/27 ,  H01L2224/11 ,  H01L2224/83 ,  H01L2224/81

Abstract: A method for manufacturing metal powder comprising: providing a basic metal salt solution; contacting the basic metal salt solution with a reducing agent to precipitate metal powder therefrom; and recovering precipitated metal powder from the solvent.

Abstract translation: 一种制造金属粉末的方法，包括：提供碱金属盐溶液; 使碱金属盐溶液与还原剂接触以从其中沉淀金属粉末; 并从溶剂中回收沉淀的金属粉末。

公开(公告)号：US20160343692A1

公开(公告)日：2016-11-24

申请号：US15230921

申请日：2016-08-08

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chun-Cheng Lin ,  Chung-Shi Liu ,  Kuei-Wei Huang ,  Cheng-Ting Chen ,  Wei-Hung Lin ,  Ming-Da Cheng

IPC: H01L25/065 ,  H01L23/498 ,  H01L21/56 ,  H01L21/48 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L21/0273 ,  H01L21/486 ,  H01L21/56 ,  H01L21/76898 ,  H01L23/3128 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49866 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0231 ,  H01L2224/0239 ,  H01L2224/03452 ,  H01L2224/0401 ,  H01L2224/05083 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05184 ,  H01L2224/1131 ,  H01L2224/11424 ,  H01L2224/1152 ,  H01L2224/1162 ,  H01L2224/11825 ,  H01L2224/11849 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13118 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13611 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06586 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01048 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15747 ,  H01L2924/18161 ,  H01L2924/2064 ,  H01L2924/20641 ,  H01L2924/20642 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A system and method for packaging semiconductor dies is provided. An embodiment comprises a first package with a first contact and a second contact. A post-contact material is formed on the first contact in order to adjust the height of a joint between the contact pad a conductive bump. In another embodiment a conductive pillar is utilized to control the height of the joint between the contact pad and external connections.