公开(公告)号：US10748803B2

公开(公告)日：2020-08-18

申请号：US16390248

申请日：2019-04-22

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yan-Zuo Tsai ,  Yang-Chih Hsueh ,  Chia-Yin Chen ,  Fu-Kang Tien ,  Ebin Liao ,  Wen-Chih Chiou

IPC: H01L21/66 ,  H01L23/00 ,  H01L21/683 ,  H01L21/67

Abstract: A method and apparatus for bonding semiconductor devices are disclosed. In an embodiment, the method may include attaching a first die to a flip head of a flip module, flipping the first die with the flip module, removing the first die from the flip module after flipping the first die, inspecting the flip head of the flip module for contamination after removing the first die, cleaning the flip head with an in situ cleaning module after inspecting the flip head, and attaching a second die to the flip head after cleaning the flip head.

公开(公告)号：US20230063851A1

公开(公告)日：2023-03-02

申请号：US17461971

申请日：2021-08-30

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： I-Chun Hsu ,  Yan-Zuo Tsai ,  Chia-Yin Chen ,  Yang-Chih Hsueh ,  Yung-Chi Lin ,  Tsang-Jiuh Wu ,  Wen-Chih Chiou

IPC: H01L25/065 ,  H01L25/18 ,  H01L25/00

Abstract: Provided are a semiconductor device and a method for manufacturing the same, and a semiconductor package. The semiconductor device includes a die stack and a cap substrate. The die stack includes a first die, second dies stacked on the first die, and a third die stacked on the second dies. The first die includes first through semiconductor vias. Each of the second dies include second through semiconductor vias. The third die includes third through semiconductor vias. The cap substrate is disposed on the third die of the die stack. A sum of a thickness of the third die and a thickness of the cap substrate ranges from about 50 μm to about 80 μm.

公开(公告)号：US20170271242A1

公开(公告)日：2017-09-21

申请号：US15614339

申请日：2017-06-05

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hsiao Yun Lo ,  Yung-Chi Lin ,  Yang-Chih Hsueh ,  Tsang-Jiuh Wu ,  Wen-Chih Chiou

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/00 ,  H01L23/532 ,  H01L21/288 ,  H01L23/525

CPC classification number: H01L23/481 ,  H01L21/2885 ,  H01L21/76847 ,  H01L21/7685 ,  H01L21/76885 ,  H01L21/76898 ,  H01L23/525 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/53242 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L29/43 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/0347 ,  H01L2224/03616 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05005 ,  H01L2224/05018 ,  H01L2224/05023 ,  H01L2224/05025 ,  H01L2224/05026 ,  H01L2224/05099 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05157 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/0518 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05541 ,  H01L2224/05552 ,  H01L2224/05567 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/0558 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/0568 ,  H01L2224/05681 ,  H01L2224/1131 ,  H01L2224/1134 ,  H01L2224/11849 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2924/00 ,  H01L2924/00011 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/207

Abstract: An interconnection structure and method disclosed for providing an interconnection structure that includes conductive features having reduced topographic variations. The interconnection structure includes a contact pad disposed over a substrate. The contact pad includes a first layer of a first conductive material and a second layer of a second conductive material over the first layer. The first conductive material and the second conductive material are made of substantially the same material and have a first average grain size and a second average grain size that is smaller than the first average grain size. The interconnection structure also includes a passivation layer covering the substrate and the contact pad, and the passivation layer has an opening exposing the contact pad.

公开(公告)号：US09673132B2

公开(公告)日：2017-06-06

申请号：US14511006

申请日：2014-10-09

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hsiao Yun Lo ,  Yung-Chi Lin ,  Yang-Chih Hsueh ,  Tsang-Jiuh Wu ,  Wen-Chih Chiou

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/00 ,  H01L23/532 ,  H01L21/288 ,  H01L23/525

CPC classification number: H01L23/481 ,  H01L21/2885 ,  H01L21/7685 ,  H01L21/76885 ,  H01L21/76898 ,  H01L23/525 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/53242 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/0347 ,  H01L2224/03616 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05005 ,  H01L2224/05018 ,  H01L2224/05023 ,  H01L2224/05025 ,  H01L2224/05026 ,  H01L2224/05099 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05157 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/0518 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05541 ,  H01L2224/05567 ,  H01L2224/05568 ,  H01L2224/05571 ,  H01L2224/0558 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/0568 ,  H01L2224/05681 ,  H01L2224/05684 ,  H01L2224/1131 ,  H01L2224/1134 ,  H01L2224/11849 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/00012 ,  H01L2924/207 ,  H01L2224/05552 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2224/81805

Abstract: An interconnection structure and method disclosed for providing an interconnection structure that includes conductive features having reduced topographic variations. The interconnection structure includes a contact pad disposed over a substrate. The contact pad includes a first layer of a first conductive material and a second layer of a second conductive material over the first layer. The first conductive material and the second conductive material are made of substantially the same material and have a first average grain size and a second average grain size that is smaller than the first average grain size. The interconnection structure also includes a passivation layer covering the substrate and the contact pad, and the passivation layer has an opening exposing the contact pad.

公开(公告)号：US20150054174A1

公开(公告)日：2015-02-26

申请号：US14511006

申请日：2014-10-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Hsiao Yun Lo ,  Yung-Chi Lin ,  Yang-Chih Hsueh ,  Tsang-Jiuh Wu ,  Wen-Chih Chiou

IPC: H01L23/48 ,  H01L21/768

CPC classification number: H01L23/481 ,  H01L21/2885 ,  H01L21/7685 ,  H01L21/76885 ,  H01L21/76898 ,  H01L23/525 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/53242 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/0347 ,  H01L2224/03616 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05005 ,  H01L2224/05018 ,  H01L2224/05023 ,  H01L2224/05025 ,  H01L2224/05026 ,  H01L2224/05099 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05157 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/0518 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05541 ,  H01L2224/05567 ,  H01L2224/05568 ,  H01L2224/05571 ,  H01L2224/0558 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/0568 ,  H01L2224/05681 ,  H01L2224/05684 ,  H01L2224/1131 ,  H01L2224/1134 ,  H01L2224/11849 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/00012 ,  H01L2924/207 ,  H01L2224/05552 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2224/81805

Abstract: An interconnection structure and method disclosed for providing an interconnection structure that includes conductive features having reduced topographic variations. The interconnection structure includes a contact pad disposed over a substrate. The contact pad includes a first layer of a first conductive material and a second layer of a second conductive material over the first layer. The first conductive material and the second conductive material are made of substantially the same material and have a first average grain size and a second average grain size that is smaller than the first average grain size. The interconnection structure also includes a passivation layer covering the substrate and the contact pad, and the passivation layer has an opening exposing the contact pad.

Abstract translation: 公开了一种用于提供包括具有减小的地形变化的导电特征的互连结构的互连结构和方法。 互连结构包括设置在衬底上的接触焊盘。 接触焊盘包括在第一层上的第一导电材料的第一层和第二导电材料的第二层。 第一导电材料和第二导电材料由基本相同的材料制成，并且具有小于第一平均晶粒尺寸的第一平均晶粒尺寸和第二平均晶粒尺寸。 互连结构还包括覆盖衬底和接触焊盘的钝化层，并且钝化层具有露出接触焊盘的开口。

公开(公告)号：US11948920B2

公开(公告)日：2024-04-02

申请号：US17461971

申请日：2021-08-30

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： I-Chun Hsu ,  Yan-Zuo Tsai ,  Chia-Yin Chen ,  Yang-Chih Hsueh ,  Yung-Chi Lin ,  Tsang-Jiuh Wu ,  Wen-Chih Chiou

IPC: H01L25/18 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L25/0657 ,  H01L25/0652 ,  H01L25/18 ,  H01L25/50 ,  H01L2225/06524 ,  H01L2225/06544 ,  H01L2225/06565

Abstract: Provided are a semiconductor device and a method for manufacturing the same, and a semiconductor package. The semiconductor device includes a die stack and a cap substrate. The die stack includes a first die, second dies stacked on the first die, and a third die stacked on the second dies. The first die includes first through semiconductor vias. Each of the second dies include second through semiconductor vias. The third die includes third through semiconductor vias. The cap substrate is disposed on the third die of the die stack. A sum of a thickness of the third die and a thickness of the cap substrate ranges from about 50 μm to about 80 μm.

公开(公告)号：US20190244851A1

公开(公告)日：2019-08-08

申请号：US16390248

申请日：2019-04-22

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yan-Zuo Tsai ,  Yang-Chih Hsueh ,  Chia-Yin Chen ,  Fu-Kang Tien ,  Ebin Liao ,  Wen-Chih Chiou

IPC: H01L21/683 ,  H01L23/00 ,  H01L21/66

Abstract: A method and apparatus for bonding semiconductor devices are disclosed. In an embodiment, the method may include attaching a first die to a flip head of a flip module, flipping the first die with the flip module, removing the first die from the flip module after flipping the first die, inspecting the flip head of the flip module for contamination after removing the first die, cleaning the flip head with an in situ cleaning module after inspecting the flip head, and attaching a second die to the flip head after cleaning the flip head.

公开(公告)号：US10269611B1

公开(公告)日：2019-04-23

申请号：US15925206

申请日：2018-03-19

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yan-Zuo Tsai ,  Yang-Chih Hsueh ,  Chia-Yin Chen ,  Fu-Kang Tien ,  Ebin Liao ,  Wen-Chih Chiou

IPC: H01L21/683 ,  H01L21/66 ,  H01L23/00

Abstract: A method and apparatus for bonding semiconductor devices are disclosed. In an embodiment, the method may include attaching a first die to a flip head of a flip module, flipping the first die with the flip module, removing the first die from the flip module after flipping the first die, inspecting the flip head of the flip module for contamination after removing the first die, cleaning the flip head with an in situ cleaning module after inspecting the flip head, and attaching a second die to the flip head after cleaning the flip head.

公开(公告)号：US10032698B2

公开(公告)日：2018-07-24

申请号：US15614339

申请日：2017-06-05

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hsiao Yun Lo ,  Yung-Chi Lin ,  Yang-Chih Hsueh ,  Tsang-Jiuh Wu ,  Wen-Chih Chiou

IPC: H01L23/48 ,  H01L23/50 ,  H01L21/44 ,  H01L21/768 ,  H01L23/532 ,  H01L23/00 ,  H01L21/288 ,  H01L23/525

Abstract: An interconnection structure and method disclosed for providing an interconnection structure that includes conductive features having reduced topographic variations. The interconnection structure includes a contact pad disposed over a substrate. The contact pad includes a first layer of a first conductive material and a second layer of a second conductive material over the first layer. The first conductive material and the second conductive material are made of substantially the same material and have a first average grain size and a second average grain size that is smaller than the first average grain size. The interconnection structure also includes a passivation layer covering the substrate and the contact pad, and the passivation layer has an opening exposing the contact pad.