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公开(公告)号：US20240363593A1
公开(公告)日：2024-10-31
申请号：US18767883
申请日：2024-07-09
发明人： Chen-Hua Yu , Wen-Chih Chiou
IPC分类号： H01L25/065 , H01L21/56 , H01L21/822 , H01L23/00 , H01L23/31 , H01L23/532 , H01L23/538 , H01L25/00
CPC分类号： H01L25/0657 , H01L21/563 , H01L21/8221 , H01L23/3114 , H01L23/3128 , H01L23/3185 , H01L23/53295 , H01L23/5384 , H01L24/32 , H01L25/50 , H01L2224/0401
摘要： A semiconductor device including a first integrated circuit component, a second integrated circuit component, a third integrated circuit component, and a dielectric encapsulation is provided. The second integrated circuit component is stacked on and electrically coupled to the first integrated circuit component, and the third integrated circuit component is stacked on and electrically coupled to the second integrated circuit component. The dielectric encapsulation is disposed on the second integrated circuit component and laterally encapsulating the third integrated circuit component, where outer sidewalls of the dielectric encapsulation are substantially aligned with sidewalls of the first and second integrated circuit components. A manufacturing method of the above-mentioned semiconductor device is also provided.
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公开(公告)号：US12062640B2
公开(公告)日：2024-08-13
申请号：US18167867
申请日：2023-02-12
发明人： Chen-Hua Yu , Wen-Chih Chiou
IPC分类号： H01L25/065 , H01L21/56 , H01L21/822 , H01L23/00 , H01L23/31 , H01L23/532 , H01L23/538 , H01L25/00
CPC分类号： H01L25/0657 , H01L21/563 , H01L21/8221 , H01L23/3114 , H01L23/3128 , H01L23/3185 , H01L23/53295 , H01L23/5384 , H01L24/32 , H01L25/50 , H01L2224/0401
摘要： A semiconductor device including a first integrated circuit component, a second integrated circuit component, a third integrated circuit component, and a dielectric encapsulation is provided. The second integrated circuit component is stacked on and electrically coupled to the first integrated circuit component, and the third integrated circuit component is stacked on and electrically coupled to the second integrated circuit component. The dielectric encapsulation is disposed on the second integrated circuit component and laterally encapsulating the third integrated circuit component, where outer sidewalls of the dielectric encapsulation are substantially aligned with sidewalls of the first and second integrated circuit components. A manufacturing method of the above-mentioned semiconductor device is also provided.
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公开(公告)号：US11948920B2
公开(公告)日：2024-04-02
申请号：US17461971
申请日：2021-08-30
发明人： I-Chun Hsu , Yan-Zuo Tsai , Chia-Yin Chen , Yang-Chih Hsueh , Yung-Chi Lin , Tsang-Jiuh Wu , Wen-Chih Chiou
IPC分类号： H01L25/18 , H01L25/00 , H01L25/065
CPC分类号： H01L25/0657 , H01L25/0652 , H01L25/18 , H01L25/50 , H01L2225/06524 , H01L2225/06544 , H01L2225/06565
摘要： Provided are a semiconductor device and a method for manufacturing the same, and a semiconductor package. The semiconductor device includes a die stack and a cap substrate. The die stack includes a first die, second dies stacked on the first die, and a third die stacked on the second dies. The first die includes first through semiconductor vias. Each of the second dies include second through semiconductor vias. The third die includes third through semiconductor vias. The cap substrate is disposed on the third die of the die stack. A sum of a thickness of the third die and a thickness of the cap substrate ranges from about 50 μm to about 80 μm.
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公开(公告)号：US20240055315A1
公开(公告)日：2024-02-15
申请号：US17886466
申请日：2022-08-12
发明人： Chih-Wei Wu , Ying-Ching Shih , An-Jhih Su , Wen-Chih Chiou
IPC分类号： H01L23/367 , H01L23/31 , H01L25/065 , H01L23/373 , H01L25/00 , H01L21/56 , H01L23/00
CPC分类号： H01L23/367 , H01L23/3121 , H01L25/0655 , H01L23/3738 , H01L25/50 , H01L21/561 , H01L24/97 , H01L2224/97
摘要： Disclosed are a semiconductor package and a manufacturing method of a semiconductor package. In one embodiment, the semiconductor package includes an interposer substrate, a plurality of semiconductor dies, one or more heat dissipation elements and an encapsulant. The plurality of semiconductor dies are disposed on the interposer substrate. The one or more heat dissipation elements are disposed on the plurality of semiconductor dies. The encapsulant is disposed on the interposer substrate and surrounds the plurality of semiconductor dies and the one or more heat dissipation elements.
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公开(公告)号：US11855042B2
公开(公告)日：2023-12-26
申请号：US17696591
申请日：2022-03-16
发明人： Ming-Fa Chen , Wen-Chih Chiou , Sung-Feng Yeh
IPC分类号： H01L25/065 , H01L23/31 , H01L23/48 , H01L23/00 , H01L25/00 , H01L21/56 , H01L23/538 , H01L25/10
CPC分类号： H01L25/0655 , H01L21/565 , H01L23/3121 , H01L23/3142 , H01L23/481 , H01L23/5386 , H01L24/13 , H01L24/16 , H01L24/24 , H01L24/73 , H01L25/0652 , H01L25/50 , H01L23/3128 , H01L24/32 , H01L24/81 , H01L24/92 , H01L25/105 , H01L2224/0231 , H01L2224/02379 , H01L2224/13024 , H01L2224/16227 , H01L2224/18 , H01L2224/24137 , H01L2224/32225 , H01L2224/73204 , H01L2224/73259 , H01L2224/80001 , H01L2225/06541 , H01L2225/06548 , H01L2225/06565 , H01L2924/15192
摘要： A method of manufacturing a semiconductor structure includes following operations. A substrate is provided. A first die is disposed over the substrate. A second die is provided. The second die includes a via extended within the second die. The second die is disposed over the substrate. A molding is formed around the first die and second die. An interconnect structure is formed. The interconnect structure includes a dielectric layer and a conductive member. The dielectric layer is disposed over the molding, the first die and the second die. The conductive member is surrounded by the dielectric layer. The via is formed by removing a portion of the second die to form a recess extended within the second die and disposing a conductive material into the recess.
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公开(公告)号：US11830861B2
公开(公告)日：2023-11-28
申请号：US17029065
申请日：2020-09-23
发明人： Yu-Kuang Liao , Cheng-Chun Tsai , Chen-Hua Yu , Fang-Cheng Chen , Wen-Chih Chiou , Ping-Jung Wu
CPC分类号： H01L25/167 , G02B6/1225 , G02B6/1226 , G02B6/4201 , H01L23/29 , H01L23/5226 , H01L24/17 , H04B10/40
摘要： A semiconductor package includes a first optical transceiver, a second optical transceiver, a third optical transceiver, and a plasmonic waveguide. The first optical transceiver, the second optical transceiver, and the third optical transceiver are stacked in sequential order. The first optical transceiver and the third optical transceiver respectively at least one optical input/output portion for transmitting and receiving an optical signal. The plasmonic waveguide includes a first segment, a second segment, and a third segment optically coupled to one another. The first segment is embedded in the first optical transceiver. The second segment extends through the second optical transceiver. The third segment is embedded in the third optical transceiver. The first segment is optically coupled to the at least one optical input/output portion of the first optical transceiver and the third segment is optically coupled to the at least one optical input/output portion of the third optical transceiver.
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公开(公告)号：US20230142163A1
公开(公告)日：2023-05-11
申请号：US18152089
申请日：2023-01-09
发明人： Chen-Yu Tsai , Ku-Feng Yang , Wen-Chih Chiou
CPC分类号： C25D21/04 , C25D7/123 , C25D17/001 , C25D17/08 , C25D21/10 , H01L21/7684 , H01L21/76898
摘要： A plating apparatus includes a workpiece holder, a plating bath, and a clamp ring. The plating bath is underneath the workpiece holder. The clamp ring is connected to the workpiece holder. The clamp ring includes channels communicating an inner surface of the clamp ring and an outer surface of the clamp ring.
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公开(公告)号：US11610866B2
公开(公告)日：2023-03-21
申请号：US17227378
申请日：2021-04-12
发明人： Chen-Hua Yu , Wen-Chih Chiou
IPC分类号： H01L25/065 , H01L23/532 , H01L23/31 , H01L23/00 , H01L21/822 , H01L25/00 , H01L23/538 , H01L21/56
摘要： A semiconductor device including a first integrated circuit component, a second integrated circuit component, a third integrated circuit component, and a dielectric encapsulation is provided. The second integrated circuit component is stacked on and electrically coupled to the first integrated circuit component, and the third integrated circuit component is stacked on and electrically coupled to the second integrated circuit component. The dielectric encapsulation is disposed on the second integrated circuit component and laterally encapsulating the third integrated circuit component, where outer sidewalls of the dielectric encapsulation are substantially aligned with sidewalls of the first and second integrated circuit components. A manufacturing method of the above-mentioned semiconductor device is also provided.
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公开(公告)号：US11585005B2
公开(公告)日：2023-02-21
申请号：US17147471
申请日：2021-01-13
发明人： Chen-Yu Tsai , Ku-Feng Yang , Wen-Chih Chiou
摘要： A semiconductor apparatus and methods of processing a semiconductor workpiece are provided. The semiconductor apparatus for pre-wetting a semiconductor workpiece includes a process chamber, a workpiece holder disposed within the process chamber to hold the semiconductor workpiece, a pre-wetting fluid tank disposed outside the process chamber and containing a pre-wetting fluid, and a conduit coupled to the pre-wetting fluid tank and extending into the process chamber. The conduit delivers the pre-wetting fluid from the pre-wetting fluid tank out through an outlet of the conduit to wet a major surface of the semiconductor workpiece comprising a plurality of recess portions.
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公开(公告)号：US20230021005A1
公开(公告)日：2023-01-19
申请号：US17738014
申请日：2022-05-06
发明人： Wen-Chih Chiou , Ping-Yin Hsieh , Ying-Ching Shih , Pu Wang , Li-Hui Cheng , Yi-Huan Liao , Chih-Hao Chen
IPC分类号： H01L23/367 , H01L21/48 , H01L25/065
摘要： A semiconductor device includes a substrate, a package structure, a thermal interface material (TIM) structure, and a lid structure. The package structure is disposed on the substrate. The TIM structure is disposed on the package structure. The TIM structure includes a metallic TIM layer and a non-metallic TIM layer in contact with the metallic TIM layer, and the non-metallic TIM layer surrounds the metallic TIM layer. The lid structure is disposed on the substrate and the TIM structure.
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