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    Formation of silicide contacts in semiconductor devices
    1.
    发明授权
    Formation of silicide contacts in semiconductor devices 有权

    公开(公告)号：US11081563B2

    公开(公告)日：2021-08-03

    申请号：US14839597

    申请日：2015-08-28

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Yan-Ming Tsai ,  Wei-Jung Lin ,  Fang-Cheng Chen ,  Chii-Ming Wu

    IPC分类号： H01L29/45 ,  H01L27/092 ,  H01L29/16 ,  H01L29/161 ,  H01L21/324 ,  H01L21/8238 ,  H01L21/285 ,  H01L21/265 ,  H01L29/417 ,  H01L29/66 ,  H01L21/768

    摘要： Methods of forming silicide contacts in semiconductor devices are presented. An exemplary method comprises providing a semiconductor substrate having an n-type field effect transistor (nFET) region and on a p-type field effect transistor (pFET) region; performing a pre-amorphized implantation (PAI) process to an n-type doped silicon (Si) feature in on the nFET region and a p-type doped silicon germanium (SiGe) feature in the pFET region, thereby forming an n-type amorphous silicon (a-Si) feature and a p-type amorphous silicon germanium (a-SiGe) feature; depositing a metal layer over each of the a-Si and a-SiGe features; performing an annealing process on the semiconductor device with a temperature ramp-up rate tuned according to a silicide growth rate difference between the n-type a-Si and the p-type a-SiGe features. During the annealing process the n-type a-Si and the p-type a-SiGe features are completely consumed, and amorphous silicide features are formed in the nFET and pFET regions.

    IMPROVED FORMATION OF SILICIDE CONTACTS IN SEMICONDUCTOR DEVICES
    2.
    发明申请
    IMPROVED FORMATION OF SILICIDE CONTACTS IN SEMICONDUCTOR DEVICES 审中-公开
    改进在半导体器件中形成硅化物接触

    公开(公告)号：US20150380509A1

    公开(公告)日：2015-12-31

    申请号：US14839597

    申请日：2015-08-28

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Yan-Ming Tsai ,  Wei-Jung Lin ,  Fang-Cheng Chen ,  Chii-Ming Wu

    IPC分类号： H01L29/45 ,  H01L29/16 ,  H01L29/161 ,  H01L27/092

    CPC分类号： H01L29/456 ,  H01L21/26506 ,  H01L21/28518 ,  H01L21/324 ,  H01L21/76814 ,  H01L21/76831 ,  H01L21/823814 ,  H01L27/092 ,  H01L27/0922 ,  H01L29/16 ,  H01L29/161 ,  H01L29/41725 ,  H01L29/45 ,  H01L29/6659

    摘要： Methods of forming silicide contacts in semiconductor devices are presented. An exemplary method comprises providing a semiconductor substrate having an n-type field effect transistor (nFET) region and on a p-type field effect transistor (pFET) region; performing a pre-amorphized implantation (PAI) process to an n-type doped silicon (Si) feature in on the nFET region and a p-type doped silicon germanium (SiGe) feature in the pFET region, thereby forming an n-type amorphous silicon (a-Si) feature and a p-type amorphous silicon germanium (a-SiGe) feature; depositing a metal layer over each of the a-Si and a-SiGe features; performing an annealing process on the semiconductor device with a temperature ramp-up rate tuned according to a silicide growth rate difference between the n-type a-Si and the p-type a-SiGe features. During the annealing process the n-type a-Si and the p-type a-SiGe features are completely consumed, and amorphous silicide features are formed in the nFET and pFET regions.

    摘要翻译： 介绍了在半导体器件中形成硅化物触点的方法。 一种示例性方法包括提供具有n型场效应晶体管（nFET）区域和p型场效应晶体管（pFET）区域的半导体衬底; 对nFET区中的n型掺杂硅（Si）特征和pFET区中的p型掺杂硅锗（SiGe）特征进行预非晶化注入（PAI）工艺，从而形成n型非晶态 硅（a-Si）特征和p型非晶硅锗（a-SiGe）特征; 在a-Si和a-SiGe特征的每一个上沉积金属层; 根据n型a-Si和p型a-SiGe特征之间的硅化物生长速率差调整温度上升速率对半导体器件执行退火处理。 在退火过程中，n型a-Si和p型a-SiGe特征被完全消耗，并且在nFET和pFET区域中形成无定形硅化物特征。

    Formation Of Silicide Contacts In Semiconductor Devices
    3.
    发明申请
    Formation Of Silicide Contacts In Semiconductor Devices 有权
    半导体器件中硅化物接触的形成

    公开(公告)号：US20150206881A1

    公开(公告)日：2015-07-23

    申请号：US14157927

    申请日：2014-01-17

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Yan-Ming Tsai ,  Wei-Jung Lin ,  Fang-Cheng Chen ,  Chii-Ming Wu

    IPC分类号： H01L27/092 ,  H01L21/8238 ,  H01L21/265 ,  H01L29/16 ,  H01L29/161 ,  H01L21/285 ,  H01L21/324 ,  H01L29/45

    CPC分类号： H01L29/456 ,  H01L21/26506 ,  H01L21/28518 ,  H01L21/324 ,  H01L21/76814 ,  H01L21/76831 ,  H01L21/823814 ,  H01L27/092 ,  H01L27/0922 ,  H01L29/16 ,  H01L29/161 ,  H01L29/41725 ,  H01L29/45 ,  H01L29/6659

    摘要： Methods of forming silicide contacts in semiconductor devices are presented. An exemplary method comprises providing a semiconductor substrate having an n-type field effect transistor (nFET) region and a p-type field effect transistor (pFET) region; performing a pre-amorphized implantation (PAI) process to an n-type doped silicon (Si) feature in on the nFET region and a p-type doped silicon germanium (SiGe) feature in the pFET region, thereby forming an n-type amorphous silicon (a-Si) feature and a p-type amorphous silicon germanium (a-SiGe) feature; depositing a metal layer over each of the a-Si and a-SiGe features; performing an annealing process on the semiconductor device with a temperature ramp-up rate tuned according to a silicide growth rate difference between the n-type a-Si and the p-type a-SiGe features. During the annealing process the n-type a-Si and the p-type a-SiGe features are completely consumed, and amorphous silicide features are formed in the nFET and pFET regions.

    摘要翻译： 介绍了在半导体器件中形成硅化物触点的方法。 一种示例性方法包括提供具有n型场效应晶体管（nFET）区域和p型场效应晶体管（pFET）区域的半导体衬底; 对nFET区中的n型掺杂硅（Si）特征和pFET区中的p型掺杂硅锗（SiGe）特征进行预非晶化注入（PAI）工艺，从而形成n型非晶态 硅（a-Si）特征和p型非晶硅锗（a-SiGe）特征; 在a-Si和a-SiGe特征的每一个上沉积金属层; 根据n型a-Si和p型a-SiGe特征之间的硅化物生长速率差调整温度上升速率对半导体器件执行退火处理。 在退火过程中，n型a-Si和p型a-SiGe特征被完全消耗，并且在nFET和pFET区域中形成无定形硅化物特征。

    SEMICONDUCTOR PACKAGE
    5.
    发明申请
    SEMICONDUCTOR PACKAGE 有权

    公开(公告)号：US20210005591A1

    公开(公告)日：2021-01-07

    申请号：US17029065

    申请日：2020-09-23

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Yu-Kuang Liao ,  Cheng-Chun Tsai ,  Chen-Hua Yu ,  Fang-Cheng Chen ,  Wen-Chih Chiou ,  Ping-Jung Wu

    IPC分类号： H01L25/16 ,  G02B6/122 ,  H04B10/40 ,  H01L23/00 ,  H01L23/29 ,  H01L23/522 ,  G02B6/42

    摘要： A semiconductor package includes a first optical transceiver, a second optical transceiver, a third optical transceiver, and a plasmonic waveguide. The first optical transceiver, the second optical transceiver, and the third optical transceiver are stacked in sequential order. The first optical transceiver and the third optical transceiver respectively at least one optical input/output portion for transmitting and receiving an optical signal. The plasmonic waveguide includes a first segment, a second segment, and a third segment optically coupled to one another. The first segment is embedded in the first optical transceiver. The second segment extends through the second optical transceiver. The third segment is embedded in the third optical transceiver. The first segment is optically coupled to the at least one optical input/output portion of the first optical transceiver and the third segment is optically coupled to the at least one optical input/output portion of the third optical transceiver.

    Formation of silicide contacts in semiconductor devices
    9.
    发明授权
    Formation of silicide contacts in semiconductor devices 有权
    在半导体器件中形成硅化物触点

    公开(公告)号：US09129842B2

    公开(公告)日：2015-09-08

    申请号：US14157927

    申请日：2014-01-17

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Yan-Ming Tsai ,  Wei-Jung Lin ,  Fang-Cheng Chen ,  Chii-Ming Wu

    IPC分类号： H01L21/8238 ,  H01L27/092 ,  H01L21/324 ,  H01L29/45 ,  H01L29/16 ,  H01L29/161 ,  H01L21/285 ,  H01L21/265

    CPC分类号： H01L29/456 ,  H01L21/26506 ,  H01L21/28518 ,  H01L21/324 ,  H01L21/76814 ,  H01L21/76831 ,  H01L21/823814 ,  H01L27/092 ,  H01L27/0922 ,  H01L29/16 ,  H01L29/161 ,  H01L29/41725 ,  H01L29/45 ,  H01L29/6659

    摘要： Methods of forming silicide contacts in semiconductor devices are presented. An exemplary method comprises providing a semiconductor substrate having an n-type field effect transistor (nFET) region and a p-type field effect transistor (pFET) region; performing a pre-amorphized implantation (PAI) process to an n-type doped silicon (Si) feature in on the nFET region and a p-type doped silicon germanium (SiGe) feature in the pFET region, thereby forming an n-type amorphous silicon (a-Si) feature and a p-type amorphous silicon germanium (a-SiGe) feature; depositing a metal layer over each of the a-Si and a-SiGe features; performing an annealing process on the semiconductor device with a temperature ramp-up rate tuned according to a silicide growth rate difference between the n-type a-Si and the p-type a-SiGe features. During the annealing process the n-type a-Si and the p-type a-SiGe features are completely consumed, and amorphous silicide features are formed in the nFET and pFET regions.

    摘要翻译： 介绍了在半导体器件中形成硅化物触点的方法。 一种示例性方法包括提供具有n型场效应晶体管（nFET）区域和p型场效应晶体管（pFET）区域的半导体衬底; 对nFET区中的n型掺杂硅（Si）特征和pFET区中的p型掺杂硅锗（SiGe）特征进行预非晶化注入（PAI）工艺，从而形成n型非晶态 硅（a-Si）特征和p型非晶硅锗（a-SiGe）特征; 在a-Si和a-SiGe特征的每一个上沉积金属层; 根据n型a-Si和p型a-SiGe特征之间的硅化物生长速率差调整温度上升速率对半导体器件执行退火处理。 在退火过程中，n型a-Si和p型a-SiGe特征被完全消耗，并且在nFET和pFET区域中形成无定形硅化物特征。