PLATE DESIGN TO DECREASE NOISE IN SEMICONDUCTOR DEVICES

    公开(公告)号:US20210376100A1

    公开(公告)日:2021-12-02

    申请号:US17405307

    申请日:2021-08-18

    摘要: A semiconductor device and method for forming the semiconductor device are provided. In some embodiments, a semiconductor substrate comprises a device region. An isolation structure extends laterally in a closed path to demarcate the device region. A first source/drain region and a second source/drain region are in the device region and laterally spaced. A sidewall of the first source/drain region directly contacts the isolation structure at a first isolation structure sidewall, and remaining sidewalls of the first source/drain region are spaced from the isolation structure. A selectively-conductive channel is in the device region, and extends laterally from the first source/drain region to the second source/drain region. A plate comprises a central portion and a first peripheral portion. The central portion overlies the selectively-conductive channel, and the first peripheral portion protrudes from the central portion towards the first isolation structure sidewall.

    Sensor in an internet-of-things and manufacturing method of the same

    公开(公告)号:US10508345B2

    公开(公告)日:2019-12-17

    申请号:US14879018

    申请日:2015-10-08

    IPC分类号: C23F4/00

    摘要: Some embodiments of the present disclosure provide a gas sensor in an IOT. The gas sensor includes a substrate, a conductor disposed above the substrate, and a sensing film disposed over the conductor. The conductor has a top-view pattern including a plurality of openings, a minimal dimension of the opening being less than about 4 micrometer; and a perimeter enclosing the opening. Some embodiments of the present disclosure provide a method of manufacturing a gas sensor. The method includes receiving a substrate; forming a conductor, over the substrate; patterning the conductor to form a plurality of openings in the conductor by an etching operation, and forming a gas-sensing film over the conductor. The openings are arranged in a repeating pattern, and a minimal dimension of the opening being about 4 micrometer.

    Ultra high voltage electrostatic discharge protection device with current gain
    6.
    发明授权
    Ultra high voltage electrostatic discharge protection device with current gain 有权
    具有电流增益的超高压静电放电保护装置

    公开(公告)号:US09379179B2

    公开(公告)日:2016-06-28

    申请号:US14079715

    申请日:2013-11-14

    摘要: A semiconductor device configured to provide increased current gain comprises a semiconductor substrate having a first conductivity type. The device also comprises a first semiconductor region having a second conductivity type. The device further comprises a second semiconductor region in the first semiconductor region to having the first conductivity type. The device additionally comprises a third semiconductor region in the first semiconductor region having the second conductivity type. The device also comprises a fourth semiconductor region outside the first semiconductor region having the first conductivity type. The device further comprises a fifth semiconductor region outside the first semiconductor region adjacent the fourth semiconductor region and having the second conductivity type. The device additionally comprises a first electrode electrically connected to the third semiconductor region. The device further comprises a second electrode electrically connected to the fourth semiconductor region and to the fifth semiconductor region.

    摘要翻译: 配置成提供增加的电流增益的半导体器件包括具有第一导电类型的半导体衬底。 该器件还包括具有第二导电类型的第一半导体区域。 该器件还包括在第一半导体区域中具有第一导电类型的第二半导体区域。 该器件还包括具有第二导电类型的第一半导体区域中的第三半导体区域。 该器件还包括具有第一导电类型的第一半导体区域之外的第四半导体区域。 该器件还包括与第四半导体区域相邻并具有第二导电类型的第一半导体区域外的第五半导体区域。 该装置还包括电连接到第三半导体区域的第一电极。 该器件还包括电连接到第四半导体区域和第五半导体区域的第二电极。

    BREAKDOWN VOLTAGE CAPABILITY OF HIGH VOLTAGE DEVICE

    公开(公告)号:US20230014120A1

    公开(公告)日:2023-01-19

    申请号:US17949266

    申请日:2022-09-21

    摘要: Various embodiments of the present disclosure are directed towards an integrated chip. The integrated chip includes a semiconductor substrate having a device substrate overlying a handle substrate and an insulator layer disposed between the device substrate and the handle substrate. A gate electrode overlies the device substrate between a drain region and a source region. A conductive via extends through the device substrate and the insulator layer to contact the handle substrate. A first isolation structure is disposed within the device substrate and comprises a first isolation segment disposed laterally between the gate electrode and the conductive via. A contact region is disposed within the device substrate between the first isolation segment and the conductive via. A conductive gate electrode directly overlies the first isolation segment and is electrically coupled to the contact region.

    Semiconductor device and method for manufacturing the same

    公开(公告)号:US10985256B2

    公开(公告)日:2021-04-20

    申请号:US16889781

    申请日:2020-06-01

    摘要: A semiconductor device includes a semiconductor substrate, a gate dielectric, a gate electrode, a pair of source/drain regions, a pair of first well regions, a second well region, a pair of contact regions and a pair of third well regions. The gate dielectric is disposed in the semiconductor substrate having a concave profile that defines an upper boundary lower than an upper surface of the semiconductor substrate. The gate electrode is disposed over the gate dielectric. The pair of source/drain regions are disposed on opposing sides of the gate dielectric. The pair of first well regions are disposed under the pair of source/drain regions. The second well region is disposed between the pair of first well regions. The pair of contact regions are disposed on opposing sides of the pair of source/drain regions. The pair of third well regions are disposed under the pair of contact regions.