-
公开(公告)号:US11538914B2
公开(公告)日:2022-12-27
申请号:US17224956
申请日:2021-04-07
发明人: Ta-Yuan Kung , Ruey-Hsin Liu , Chen-Liang Chu , Chih-Wen Yao , Ming-Ta Lei
IPC分类号: H01L29/423 , H01L29/78 , H01L29/66 , H01L21/762 , H01L29/06
摘要: A semiconductor device includes a semiconductor substrate, a gate dielectric, a gate electrode, and a pair of source/drain regions. The gate dielectric is disposed in the semiconductor substrate having an upper boundary lower than an upper surface of the semiconductor substrate, and an upper surface flush with the upper surface of the semiconductor substrate. The gate electrode is disposed over the gate dielectric having a first section over the upper boundary of the gate dielectric and a second section over the upper surface of the gate dielectric. The second section partially covers and partially exposes the upper surface of the gate dielectric. The pair of source/drain regions are disposed on opposing sides of the gate dielectric.
-
公开(公告)号:US11508845B2
公开(公告)日:2022-11-22
申请号:US17028796
申请日:2020-09-22
发明人: Chen-Liang Chu , Ta-Yuan Kung , Ker-Hsiao Huo , Yi-Huan Chen
IPC分类号: H01L29/78 , H01L29/10 , H01L23/522 , H01L29/06 , H01L29/66
摘要: A semiconductor structure is disclosed. The semiconductor structure includes: a substrate of a first conductivity; a first region of the first conductivity formed in the substrate; a second region of the first conductivity formed in the first region, wherein the second region has a higher doping density than the first region; a source region of a second conductivity formed in the second region; a drain region of the second conductivity formed in the substrate; a pickup region of the first conductivity formed in the second region and adjacent to the source region; and a resist protective oxide (RPO) layer formed on a top surface of the second region. An associated fabricating method is also disclosed.
-
公开(公告)号:US10930776B2
公开(公告)日:2021-02-23
申请号:US15929547
申请日:2020-05-08
发明人: Ker-Hsiao Huo , Kong-Beng Thei , Chien-Chih Chou , Yi-Min Chen , Chen-Liang Chu
摘要: A semiconductor device is provided. The semiconductor device comprises a substrate, a gate, a first doped region and a second doped region. The gate is over the substrate. The first doped region and the second doped region are in the substrate. The first doped region and the second doped region are of a same conductivity type and separated by the gate. The length of the first doped region is greater than a length of the second doped region in a direction substantially perpendicular to a channel length defined between the first doped region and the second doped region.
-
公开(公告)号:US10790387B2
公开(公告)日:2020-09-29
申请号:US15912191
申请日:2018-03-05
发明人: Ker-Hsiao Huo , Kong-Beng Thei , Chien-Chih Chou , Yi-Min Chen , Chen-Liang Chu
摘要: A semiconductor device is provided. The semiconductor device comprises a substrate, a gate, a first doped region and a second doped region. The gate is over the substrate. The first doped region and the second doped region are in the substrate. The first doped region and the second doped region are of a same conductivity type and separated by the gate. The length of the first doped region is greater than a length of the second doped region in a direction substantially perpendicular to a channel length defined between the first doped region and the second doped region.
-
公开(公告)号:US20150279951A1
公开(公告)日:2015-10-01
申请号:US14737802
申请日:2015-06-12
发明人: Chen-Liang Chu , Fei-Yun Chen , Chih-Wen Yao
IPC分类号: H01L29/423 , H01L29/40 , H01L29/78 , H01L29/66 , H01L29/06
CPC分类号: H01L29/4238 , H01L29/0619 , H01L29/0653 , H01L29/401 , H01L29/42316 , H01L29/42376 , H01L29/66477 , H01L29/66659 , H01L29/78 , H01L29/7835
摘要: The present disclosure provides an apparatus and method for fabricating a semiconductor gate. The apparatus includes, a substrate having an active region and a dielectric region that forms an interface with the active region; a gate electrode located above a portion of the active region and a portion of the dielectric region; and a dielectric material disposed within the gate electrode, the dielectric material being disposed near the interface between the active region and the dielectric region. The method includes, providing a substrate having an active region and a dielectric region that forms an interface with the active region; forming a gate electrode over the substrate, the gate electrode having an opening near a region of the gate electrode that is above the interface; and filling the opening with a dielectric material.
摘要翻译: 本公开提供了一种用于制造半导体栅极的装置和方法。 该装置包括:具有有源区和与该有源区形成界面的电介质区的衬底; 位于所述有源区的一部分上方的栅电极和所述电介质区的一部分; 以及设置在所述栅电极内的介电材料,所述电介质材料设置在所述有源区和所述电介质区之间的界面附近。 该方法包括:提供具有与活性区形成界面的有源区和电介质区的衬底; 在所述衬底上形成栅电极,所述栅电极在所述界面之上的所述栅电极的区域附近具有开口; 并用介电材料填充开口。
-
6.
公开(公告)号:US09299806B2
公开(公告)日:2016-03-29
申请号:US14715150
申请日:2015-05-18
IPC分类号: H01L21/336 , H01L29/66 , H01L29/78 , H01L29/06 , H01L29/417
CPC分类号: H01L29/66681 , H01L29/0619 , H01L29/41758 , H01L29/7823 , H01L29/7833
摘要: An integrated circuit and a method of forming is provided. The method includes forming a first well in a substrate, the first well having a first conductivity type, and forming a first source/drain region in the first well, the first source/drain region having a second conductivity type. A resistance protection ring is formed on the substrate.
摘要翻译: 提供集成电路和成形方法。 该方法包括在衬底中形成第一阱,第一阱具有第一导电类型,以及在第一阱中形成第一源极/漏极区,第一源极/漏极区具有第二导电类型。 在基板上形成电阻保护环。
-
公开(公告)号:US20240153943A1
公开(公告)日:2024-05-09
申请号:US18405159
申请日:2024-01-05
发明人: Sheng-Fu Hsu , Ta-Yuan Kung , Chen-Liang Chu , Chih-Chung Tsai
CPC分类号: H01L27/0251 , H01L21/28052 , H01L21/28097 , H01L21/28518 , H01L29/0649 , H01L29/4933 , H01L29/66659
摘要: Various embodiments of the present disclosure are directed towards a semiconductor device. The semiconductor device comprises a source region and a drain region in a substrate and laterally spaced. A gate stack is over the substrate and between the source region and the drain region. The drain region includes two or more first doped regions having a first doping type in the substrate. The drain region further includes one or more second doped regions in the substrate. The first doped regions have a greater concentration of first doping type dopants than the second doped regions, and each of the second doped regions is disposed laterally between two neighboring first doped regions.
-
公开(公告)号:US20220367655A1
公开(公告)日:2022-11-17
申请号:US17874486
申请日:2022-07-27
发明人: Chen-Liang Chu , Chien-Chih Chou , Chih-Chang Cheng , Yi-Huan Chen , Kong-Beng Thei , Ming-Ta Lei , Ruey-Hsin Liu , Ta-Yuan Kung
IPC分类号: H01L29/423 , H01L29/06 , H01L29/08 , H01L29/49 , H01L29/66 , H01L29/78 , H01L21/28 , H01L21/285 , H01L21/762 , H01L29/45
摘要: A method to form a transistor device with a recessed gate structure is provided. In one embodiment, a gate structure is formed overlying a device region and an isolation structure. The gate structure separates a device doping well along a first direction with a pair of recess regions disposed on opposite sides of the device region in a second direction perpendicular to the first direction. A pair of source/drain regions in is formed the device region on opposite sides of the gate structure. A sidewall spacer is formed extending along sidewalls of the gate structure, where a top surface of the sidewall spacer is substantially flush with the top surface of the gate structure. A resistive protection layer is then formed on the sidewall spacer and covering the pair of recess regions.
-
公开(公告)号:US09831340B2
公开(公告)日:2017-11-28
申请号:US15017197
申请日:2016-02-05
发明人: Chen-Liang Chu , Ta-Yuan Kung , Ker-Hsiao Huo , Yi-Huan Chen
IPC分类号: H01L29/78 , H01L29/06 , H01L29/66 , H01L23/522
CPC分类号: H01L29/7836 , H01L23/5226 , H01L29/0615 , H01L29/1045 , H01L29/665 , H01L29/66659 , H01L29/7835
摘要: A semiconductor structure is disclosed. The semiconductor structure includes: a substrate of a first conductivity; a first region of the first conductivity formed in the substrate; a second region of the first conductivity formed in the first region, wherein the second region has a higher doping density than the first region; a source region of a second conductivity formed in the second region; a drain region of the second conductivity formed in the substrate; a pickup region of the first conductivity formed in the second region and adjacent to the source region; and a resist protective oxide (RPO) layer formed on a top surface of the second region. An associated fabricating method is also disclosed.
-
公开(公告)号:US09466681B2
公开(公告)日:2016-10-11
申请号:US14737802
申请日:2015-06-12
IPC分类号: H01L29/423 , H01L29/78 , H01L29/06 , H01L29/66 , H01L29/40
CPC分类号: H01L29/4238 , H01L29/0619 , H01L29/0653 , H01L29/401 , H01L29/42316 , H01L29/42376 , H01L29/66477 , H01L29/66659 , H01L29/78 , H01L29/7835
摘要: The present disclosure provides an apparatus and method for fabricating a semiconductor gate. The apparatus includes, a substrate having an active region and a dielectric region that forms an interface with the active region; a gate electrode located above a portion of the active region and a portion of the dielectric region; and a dielectric material disposed within the gate electrode, the dielectric material being disposed near the interface between the active region and the dielectric region. The method includes, providing a substrate having an active region and a dielectric region that forms an interface with the active region; forming a gate electrode over the substrate, the gate electrode having an opening near a region of the gate electrode that is above the interface; and filling the opening with a dielectric material.
-
-
-
-
-
-
-
-
-