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公开(公告)号：US11538914B2
公开(公告)日：2022-12-27
申请号：US17224956
申请日：2021-04-07
发明人： Ta-Yuan Kung , Ruey-Hsin Liu , Chen-Liang Chu , Chih-Wen Yao , Ming-Ta Lei
IPC分类号： H01L29/423 , H01L29/78 , H01L29/66 , H01L21/762 , H01L29/06
摘要： A semiconductor device includes a semiconductor substrate, a gate dielectric, a gate electrode, and a pair of source/drain regions. The gate dielectric is disposed in the semiconductor substrate having an upper boundary lower than an upper surface of the semiconductor substrate, and an upper surface flush with the upper surface of the semiconductor substrate. The gate electrode is disposed over the gate dielectric having a first section over the upper boundary of the gate dielectric and a second section over the upper surface of the gate dielectric. The second section partially covers and partially exposes the upper surface of the gate dielectric. The pair of source/drain regions are disposed on opposing sides of the gate dielectric.
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公开(公告)号：US11508845B2
公开(公告)日：2022-11-22
申请号：US17028796
申请日：2020-09-22
发明人： Chen-Liang Chu , Ta-Yuan Kung , Ker-Hsiao Huo , Yi-Huan Chen
IPC分类号： H01L29/78 , H01L29/10 , H01L23/522 , H01L29/06 , H01L29/66
摘要： A semiconductor structure is disclosed. The semiconductor structure includes: a substrate of a first conductivity; a first region of the first conductivity formed in the substrate; a second region of the first conductivity formed in the first region, wherein the second region has a higher doping density than the first region; a source region of a second conductivity formed in the second region; a drain region of the second conductivity formed in the substrate; a pickup region of the first conductivity formed in the second region and adjacent to the source region; and a resist protective oxide (RPO) layer formed on a top surface of the second region. An associated fabricating method is also disclosed.
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公开(公告)号：US20220336440A1
公开(公告)日：2022-10-20
申请号：US17845121
申请日：2022-06-21
发明人： Sheng-Fu Hsu , Ta-Yuan Kung , Chen-Liang Chu , Chih-Chung Tsai
IPC分类号： H01L27/02 , H01L29/06 , H01L21/285 , H01L21/28 , H01L29/49
摘要： Various embodiments of the present disclosure are directed towards a semiconductor device. The semiconductor device comprises a source region and a drain region in a substrate and laterally spaced. A gate stack is over the substrate and between the source region and the drain region. The drain region includes two or more first doped regions having a first doping type in the substrate. The drain region further includes one or more second doped regions in the substrate. The first doped regions have a greater concentration of first doping type dopants than the second doped regions, and each of the second doped regions is disposed laterally between two neighboring first doped regions.
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公开(公告)号：US10985256B2
公开(公告)日：2021-04-20
申请号：US16889781
申请日：2020-06-01
发明人： Ta-Yuan Kung , Ruey-Hsin Liu , Chen-Liang Chu , Chih-Wen Yao , Ming-Ta Lei
IPC分类号： H01L29/423 , H01L29/78 , H01L29/66 , H01L21/762 , H01L29/06
摘要： A semiconductor device includes a semiconductor substrate, a gate dielectric, a gate electrode, a pair of source/drain regions, a pair of first well regions, a second well region, a pair of contact regions and a pair of third well regions. The gate dielectric is disposed in the semiconductor substrate having a concave profile that defines an upper boundary lower than an upper surface of the semiconductor substrate. The gate electrode is disposed over the gate dielectric. The pair of source/drain regions are disposed on opposing sides of the gate dielectric. The pair of first well regions are disposed under the pair of source/drain regions. The second well region is disposed between the pair of first well regions. The pair of contact regions are disposed on opposing sides of the pair of source/drain regions. The pair of third well regions are disposed under the pair of contact regions.
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公开(公告)号：US10686047B2
公开(公告)日：2020-06-16
申请号：US15987318
申请日：2018-05-23
发明人： Ta-Yuan Kung , Ruey-Hsin Liu , Chen-Liang Chu , Chih-Wen Yao , Ming-Ta Lei
IPC分类号： H01L29/423 , H01L29/78 , H01L29/66 , H01L21/762 , H01L29/06
摘要： A semiconductor device includes a semiconductor substrate, a gate dielectric, a gate electrode and a pair of source/drain regions. The gate dielectric is disposed in the semiconductor substrate having a concave profile that defines an upper boundary lower than an upper surface of the semiconductor substrate. The gate electrode is disposed over the gate dielectric. The pair of source/drain regions are disposed on opposing sides of the gate dielectric.
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公开(公告)号：US20240153943A1
公开(公告)日：2024-05-09
申请号：US18405159
申请日：2024-01-05
发明人： Sheng-Fu Hsu , Ta-Yuan Kung , Chen-Liang Chu , Chih-Chung Tsai
CPC分类号： H01L27/0251 , H01L21/28052 , H01L21/28097 , H01L21/28518 , H01L29/0649 , H01L29/4933 , H01L29/66659
摘要： Various embodiments of the present disclosure are directed towards a semiconductor device. The semiconductor device comprises a source region and a drain region in a substrate and laterally spaced. A gate stack is over the substrate and between the source region and the drain region. The drain region includes two or more first doped regions having a first doping type in the substrate. The drain region further includes one or more second doped regions in the substrate. The first doped regions have a greater concentration of first doping type dopants than the second doped regions, and each of the second doped regions is disposed laterally between two neighboring first doped regions.
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公开(公告)号：US20220367655A1
公开(公告)日：2022-11-17
申请号：US17874486
申请日：2022-07-27
发明人： Chen-Liang Chu , Chien-Chih Chou , Chih-Chang Cheng , Yi-Huan Chen , Kong-Beng Thei , Ming-Ta Lei , Ruey-Hsin Liu , Ta-Yuan Kung
IPC分类号： H01L29/423 , H01L29/06 , H01L29/08 , H01L29/49 , H01L29/66 , H01L29/78 , H01L21/28 , H01L21/285 , H01L21/762 , H01L29/45
摘要： A method to form a transistor device with a recessed gate structure is provided. In one embodiment, a gate structure is formed overlying a device region and an isolation structure. The gate structure separates a device doping well along a first direction with a pair of recess regions disposed on opposite sides of the device region in a second direction perpendicular to the first direction. A pair of source/drain regions in is formed the device region on opposite sides of the gate structure. A sidewall spacer is formed extending along sidewalls of the gate structure, where a top surface of the sidewall spacer is substantially flush with the top surface of the gate structure. A resistive protection layer is then formed on the sidewall spacer and covering the pair of recess regions.
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公开(公告)号：US09831340B2
公开(公告)日：2017-11-28
申请号：US15017197
申请日：2016-02-05
发明人： Chen-Liang Chu , Ta-Yuan Kung , Ker-Hsiao Huo , Yi-Huan Chen
IPC分类号： H01L29/78 , H01L29/06 , H01L29/66 , H01L23/522
CPC分类号： H01L29/7836 , H01L23/5226 , H01L29/0615 , H01L29/1045 , H01L29/665 , H01L29/66659 , H01L29/7835
摘要： A semiconductor structure is disclosed. The semiconductor structure includes: a substrate of a first conductivity; a first region of the first conductivity formed in the substrate; a second region of the first conductivity formed in the first region, wherein the second region has a higher doping density than the first region; a source region of a second conductivity formed in the second region; a drain region of the second conductivity formed in the substrate; a pickup region of the first conductivity formed in the second region and adjacent to the source region; and a resist protective oxide (RPO) layer formed on a top surface of the second region. An associated fabricating method is also disclosed.
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公开(公告)号：US20240258373A1
公开(公告)日：2024-08-01
申请号：US18162854
申请日：2023-02-01
发明人： Ta-Yuan Kung , Chen-Liang Chu , Chih-Wen Albert Yao , Fei-Yun Chen , Ming-Ta Lei , Ruey-Hsin Liu , Yu-Chang Jong
CPC分类号： H01L29/0847 , H01L21/302 , H01L29/0692 , H01L29/402 , H01L29/4983 , H01L29/66689 , H01L29/7833
摘要： An integrated chip including a first source/drain region and a second source/drain region in a semiconductor substrate and laterally spaced apart along a top surface of the substrate. A gate dielectric layer is over the substrate and extends laterally between the first source/drain region and the second source/drain region. A thickness of the gate dielectric layer along a first sidewall of the gate dielectric layer is less than an average thickness of the gate dielectric layer. A trench isolation layer extends along gate dielectric layer. A first sidewall of the trench isolation layer extends along the first sidewall of the gate dielectric layer. A gate layer is directly over the gate dielectric layer and between the first source/drain region and the second source/drain region. A first sidewall of the gate layer is directly over the gate dielectric layer and laterally setback from the first sidewall of the gate dielectric layer.
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公开(公告)号：US11916060B2
公开(公告)日：2024-02-27
申请号：US17845159
申请日：2022-06-21
发明人： Sheng-Fu Hsu , Ta-Yuan Kung , Chen-Liang Chu , Chih-Chung Tsai
CPC分类号： H01L27/0251 , H01L21/28052 , H01L21/28097 , H01L21/28518 , H01L29/0649 , H01L29/4933 , H01L29/66659
摘要： Various embodiments of the present disclosure are directed towards a semiconductor device. The semiconductor device comprises a source region and a drain region in a substrate and laterally spaced. A gate stack is over the substrate and between the source region and the drain region. The drain region includes two or more first doped regions having a first doping type in the substrate. The drain region further includes one or more second doped regions in the substrate. The first doped regions have a greater concentration of first doping type dopants than the second doped regions, and each of the second doped regions is disposed laterally between two neighboring first doped regions.
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