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公开(公告)号：US12100706B2
公开(公告)日：2024-09-24
申请号：US17816366
申请日：2022-07-29
发明人： Jhu-Min Song , Chien-Chih Chou , Kong-Beng Thei , Fu-Jier Fan
IPC分类号： H01L27/08 , H01L21/8236 , H01L27/088 , H01L29/40 , H01L29/423
CPC分类号： H01L27/0883 , H01L21/8236 , H01L29/407 , H01L29/42372
摘要： A semiconductor structure and a method for forming a semiconductor structure are provided. The semiconductor structure includes a substrate, a gate electrode, a gate dielectric layer, first protection structures, a second protection structure and an insulating layer. The gate electrode is disposed within the substrate. The gate dielectric layer is disposed within the substrate and laterally surrounds the gate electrode. The first protection structures are disposed over the gate electrode. The second protection structure is disposed over the gate dielectric layer. The insulating layer is between the second protection structure and the gate dielectric layer.
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公开(公告)号：US12021140B2
公开(公告)日：2024-06-25
申请号：US18308897
申请日：2023-04-28
发明人： Yi-Huan Chen , Chien-Chih Chou , Szu-Hsien Liu , Kong-Beng Thei , Huan-Chih Yuan , Jhu-Min Song
IPC分类号： H01L29/78 , H01L29/06 , H01L29/423 , H01L29/66
CPC分类号： H01L29/7813 , H01L29/0649 , H01L29/4236 , H01L29/66734
摘要： A semiconductor structure and a method for forming a semiconductor structure are provided. The semiconductor structure includes a substrate; a gate electrode disposed within the substrate; a gate dielectric layer disposed within the substrate and surrounding the gate electrode; a plurality of first protection structures disposed over the gate electrode; a second protection structure disposed over the gate dielectric layer and contacting the gate dielectric layer; and a pair of source/drain regions on opposing sides of the gate dielectric layer.
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公开(公告)号：US20240113187A1
公开(公告)日：2024-04-04
申请号：US18150266
申请日：2023-01-05
发明人： Jhu-Min Song , Ying-Chou Chen , Yi-Kai Ciou , Chien-Chih Chou , Fei-Yun Chen , Yu-Chang Jong , Chi-Te Lin
IPC分类号： H01L29/423 , H01L21/8234 , H01L27/088
CPC分类号： H01L29/42368 , H01L21/823431 , H01L21/823462 , H01L27/0886 , H01L29/78
摘要： The present disclosure relates to an integrated chip. The integrated chip includes a substrate having one or more interior surfaces forming a recess within an upper surface of the substrate. Source/drain regions are disposed within the substrate on opposing sides of the recess. A first gate dielectric is arranged along the one or more interior surfaces forming the recess, and a second gate dielectric is arranged on the first gate dielectric and within the recess. A gate electrode is disposed on the second gate dielectric. The second gate dielectric includes one or more protrusions that extend outward from a recessed upper surface of the second gate dielectric and that are arranged along opposing sides of the second gate dielectric.
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公开(公告)号：US20240088154A1
公开(公告)日：2024-03-14
申请号：US18515912
申请日：2023-11-21
发明人： Yi-Huan Chen , Chien-Chih Chou , Alexander Kalnitsky , Kong-Beng Thei , Ming Chyi Liu , Shih-Chung Hsiao , Jhih-Bin Chen
IPC分类号： H01L27/092 , H01L21/28 , H01L21/8238 , H01L29/06 , H01L29/51
CPC分类号： H01L27/0922 , H01L21/28008 , H01L21/823821 , H01L21/823842 , H01L21/823857 , H01L27/0924 , H01L29/0649 , H01L29/517 , H01P1/15
摘要： The present disclosure relates to an integrated circuit (IC) that includes a boundary region defined between a low voltage region and a high voltage region, and a method of formation. In some embodiments, the integrated circuit comprises an isolation structure disposed in the boundary region of the substrate. A first polysilicon component is disposed directly on an upper surface of the substrate alongside the isolation structure. A boundary dielectric layer is disposed on the isolation structure. A second polysilicon component is disposed on the sacrifice dielectric layer.
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公开(公告)号：US11855091B2
公开(公告)日：2023-12-26
申请号：US17867771
申请日：2022-07-19
发明人： Yi-Huan Chen , Chien-Chih Chou , Alexander Kalnitsky , Kong-Beng Thei , Ming Chyi Liu , Shih-Chung Hsiao , Jhih-Bin Chen
IPC分类号： H01L27/092 , H01L21/8238 , H01L29/06 , H01L21/28 , H01L29/51 , H01P1/15 , H01L23/48
CPC分类号： H01L27/0922 , H01L21/28008 , H01L21/823821 , H01L21/823842 , H01L21/823857 , H01L27/0924 , H01L29/0649 , H01L29/517 , H01L23/481 , H01P1/15
摘要： The present disclosure relates to an integrated circuit (IC) that includes a boundary region defined between a low voltage region and a high voltage region, and a method of formation. In some embodiments, the integrated circuit comprises an isolation structure disposed in the boundary region of the substrate. A first polysilicon component is disposed over the substrate alongside the isolation structure. A boundary dielectric layer is disposed on the isolation structure. A second polysilicon component is disposed on the sacrifice dielectric layer.
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公开(公告)号：US20220367655A1
公开(公告)日：2022-11-17
申请号：US17874486
申请日：2022-07-27
发明人： Chen-Liang Chu , Chien-Chih Chou , Chih-Chang Cheng , Yi-Huan Chen , Kong-Beng Thei , Ming-Ta Lei , Ruey-Hsin Liu , Ta-Yuan Kung
IPC分类号： H01L29/423 , H01L29/06 , H01L29/08 , H01L29/49 , H01L29/66 , H01L29/78 , H01L21/28 , H01L21/285 , H01L21/762 , H01L29/45
摘要： A method to form a transistor device with a recessed gate structure is provided. In one embodiment, a gate structure is formed overlying a device region and an isolation structure. The gate structure separates a device doping well along a first direction with a pair of recess regions disposed on opposite sides of the device region in a second direction perpendicular to the first direction. A pair of source/drain regions in is formed the device region on opposite sides of the gate structure. A sidewall spacer is formed extending along sidewalls of the gate structure, where a top surface of the sidewall spacer is substantially flush with the top surface of the gate structure. A resistive protection layer is then formed on the sidewall spacer and covering the pair of recess regions.
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7.发明申请公开(公告)号：US20220271146A1
公开(公告)日：2022-08-25
申请号：US17667834
申请日：2022-02-09
IPC分类号： H01L29/66 , H01L21/768 , H01L29/78
摘要： In some embodiments, a semiconductor device is provided. The semiconductor device includes a pair of source/drain regions disposed in a semiconductor substrate, where the source/drain regions are laterally spaced. A gate electrode is disposed over the semiconductor substrate between the source/drain regions. Sidewall spacers are disposed over the semiconductor substrate on opposite sides of the gate electrode. A silicide blocking structure is disposed over the sidewalls spacers, where respective sides of the source/drain regions facing the gate electrode are spaced apart from outer sides of the sidewall spacers and are substantially aligned with outer sidewalls of the silicide blocking structure.
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公开(公告)号：US10297491B2
公开(公告)日：2019-05-21
申请号：US15861090
申请日：2018-01-03
发明人： Chien-Chih Chou , Kong-Beng Thei
IPC分类号： H01L21/8242 , H01L21/762 , H01L29/423 , H01L29/66 , H01L29/78 , H01L29/06 , H01L29/10 , H01L21/761 , H01L29/40
摘要： A structure of a semiconductor includes an isolation structure in a well of a substrate. An upper surface of the isolation structure in the well of the substrate is lower than an upper surface of the substrate and an upper surface of the well. A gate electrode has a first portion over the isolation structure, and a second portion laterally adjacent to the first portion, and above the first portion.
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公开(公告)号：US10269703B2
公开(公告)日：2019-04-23
申请号：US15434644
申请日：2017-02-16
发明人： Chin-Yu Ku , Sheng-Pin Yang , Chen-Shien Chen , Hon-Lin Huang , Chien-Chih Chou , Ting-Li Yang
IPC分类号： H01L23/522 , H01L49/02 , H01L21/768 , H01L23/532
摘要： A semiconductor device includes: a first conductive line disposed on a substrate, a second conductive line disposed on the substrate, and the second conductive line separated with the first conductive line by a trench; an insulating layer disposed on the first conductive line and the second conductive line, and filled the trench between the first conductive line and the second conductive line; and a magnetic film having a first surface and a second surface opposite to the first surface, and the first surface disposed on the insulating layer; wherein the first surface has a first concave directly above the trench, and the first concave has a first obtuse angle of at least 170 degree.
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公开(公告)号：US10084032B2
公开(公告)日：2018-09-25
申请号：US15582963
申请日：2017-05-01
发明人： Wei-Li Huang , Chi-Cheng Chen , Hon-Lin Huang , Chien-Chih Chou , Chin-Yu Ku , Chen-Shien Chen
IPC分类号： H01L21/311 , H01L21/3213 , H01L49/02 , H01F41/04 , H01F27/28 , H01L27/22 , H01L23/522 , H01L23/64
CPC分类号： H01L28/10 , H01F27/2804 , H01F41/041 , H01L21/32134 , H01L21/32138 , H01L21/32139 , H01L23/5227 , H01L23/645 , H01L27/222 , H01L2924/1206
摘要： A method of manufacturing a semiconductor device and the semiconductor device are provided in which a plurality of layers with cobalt-zirconium-tantalum are formed over a semiconductor substrate, the plurality of layers are patterned, and multiple dielectric layers and conductive materials are deposited over the CZT material. Another layer of CZT material encapsulates the conductive material.
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