公开(公告)号：US12125924B2

公开(公告)日：2024-10-22

申请号：US18211032

申请日：2023-06-16

申请人： Xiaotian Yu ,  Zheng Zuo ,  Ruigang Li

发明人： Xiaotian Yu ,  Zheng Zuo ,  Ruigang Li

IPC分类号： H01L29/66 ,  H01L29/16 ,  H01L29/868 ,  H01L29/872

CPC分类号： H01L29/868 ,  H01L29/1608 ,  H01L29/66121 ,  H01L29/66143 ,  H01L29/872

摘要： A method for manufacturing a merged PiN Schottky (MPS) diode may include steps of providing a substrate having a first conductivity type; forming an epitaxial layer with the first conductivity type on top of the substrate; forming a plurality of regions with a second conductivity type under a top surface of the epitaxial layer; forming a plasma spreading layer; depositing and patterning a first Ohmic contact metal on the regions with the second conductivity type; depositing a Schottky contact metal on top of the entire epitaxial layer; and forming a second Ohmic contact metal on a backside of the substrate. In another embodiment, the step of forming a plurality of regions with a second conductivity type may include steps of depositing and patterning a mask layer on the epitaxial layer, implanting P-type dopant into the epitaxial layer, and removing the mask layer.

公开(公告)号：US12002851B2

公开(公告)日：2024-06-04

申请号：US17690842

申请日：2022-03-09

申请人： Diodes Incorporated

发明人： Tao Long ,  Pin-Hao Huang ,  Ze Rui Chen

IPC分类号： H01L29/06 ,  H01L29/04 ,  H01L29/66

CPC分类号： H01L29/0684 ,  H01L29/04 ,  H01L29/66121

摘要： A semiconductor structure includes a substrate having a first surface and a second surface opposite to the first surface. The semiconductor structure also includes a first diffusion layer disposed in the substrate and adjacent to the first surface, and a first electrode layer disposed on the first diffusion layer. The semiconductor structure further includes a second diffusion layer disposed in the substrate and adjacent to the second surface, and a plurality of diffusion regions disposed in the second diffusion layer. The semiconductor structure further includes a second electrode layer disposed on the second diffusion layer and in contact with the plurality of diffusion regions. The second diffusion layer is coupled to the plurality of diffusion regions through the second electrode layer. The substrate is sandwiched between the first electrode layer and the second electrode layer.

公开(公告)号：US11848388B1

公开(公告)日：2023-12-19

申请号：US17746385

申请日：2022-05-17

申请人： GlobalFoundries Singapore Pte. Ltd.

发明人： Jie Zeng ,  Souvick Mitra

IPC分类号： H01L29/87 ,  H01L29/06 ,  H01L29/66

CPC分类号： H01L29/87 ,  H01L29/0649 ,  H01L29/66121

摘要： Structures for a silicon-controlled rectifier and methods of forming a structure for a silicon-controlled rectifier. The structure includes a first well and a second well in a semiconductor substrate. The first well has a first conductivity type, and the second well has a second conductivity type opposite to the first conductivity type. The structure further includes a first terminal having a doped region that has a portion in the first well, and a second terminal including a second doped region that has a portion in the first well and a third doped region in the second well. The first and second doped regions have the second conductivity type, the third doped region has the first conductivity type, and the second doped region is positioned in a lateral direction between the first doped region and the third doped region.

公开(公告)号：US20230238430A1

公开(公告)日：2023-07-27

申请号：US17690842

申请日：2022-03-09

申请人： Diodes Incorporated

发明人： Tao Long ,  Pin-Hao Huang ,  Ze Rui Chen

IPC分类号： H01L29/06 ,  H01L29/04 ,  H01L29/66

CPC分类号： H01L29/0684 ,  H01L29/04 ,  H01L29/66121

摘要： A semiconductor structure includes a substrate having a first surface and a second surface opposite to the first surface. The semiconductor structure also includes a first diffusion layer disposed in the substrate and adjacent to the first surface, and a first electrode layer disposed on the first diffusion layer. The semiconductor structure further includes a second diffusion layer disposed in the substrate and adjacent to the second surface, and a plurality of diffusion regions disposed in the second diffusion layer. The semiconductor structure further includes a second electrode layer disposed on the second diffusion layer and in contact with the plurality of diffusion regions. The second diffusion layer is coupled to the plurality of diffusion regions through the second electrode layer. The substrate is sandwiched between the first electrode layer and the second electrode layer.

公开(公告)号：US20190123145A1

公开(公告)日：2019-04-25

申请号：US16216815

申请日：2018-12-11

申请人： Mitsubishi Electric Corporation

发明人： Katsumi NAKAMURA

IPC分类号： H01L29/10 ,  H01L21/265 ,  H01L29/66 ,  H01L27/06 ,  H01L29/861 ,  H01L29/36 ,  H01L21/322 ,  H01L21/225 ,  H01L29/868 ,  H01L21/266 ,  H01L21/324 ,  H01L29/739 ,  H01L29/06

CPC分类号： H01L29/1095 ,  H01L21/2253 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/3221 ,  H01L21/324 ,  H01L27/0664 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/36 ,  H01L29/402 ,  H01L29/407 ,  H01L29/66121 ,  H01L29/66348 ,  H01L29/739 ,  H01L29/7397 ,  H01L29/8611 ,  H01L29/868

摘要： The present invention relates to a vertical semiconductor device such as an IGBT or a diode which includes an N buffer layer formed in the undersurface of and adjacent to an N− drift layer. A concentration slope δ, which is derived from displacements in a depth TB (μm) and an impurity concentration CB (cm−3), from the upper surface to the lower surface in a main portion of the N buffer layer satisfies a concentration slope condition defined by {0.03≤δ≤0.7}.

公开(公告)号：US20180323338A1

公开(公告)日：2018-11-08

申请号：US15587269

申请日：2017-05-04

申请人： X Development LLC

发明人： Michael Grundmann ,  Martin F. Schubert

IPC分类号： H01L33/06 ,  H01L33/32 ,  H01L27/15 ,  H01L25/16 ,  H01L33/00 ,  H05B33/08

CPC分类号： H01L33/06 ,  H01L25/167 ,  H01L27/156 ,  H01L29/66121 ,  H01L29/66151 ,  H01L29/66219 ,  H01L29/8618 ,  H01L29/88 ,  H01L29/882 ,  H01L33/0008 ,  H01L33/0025 ,  H01L33/0045 ,  H01L33/0075 ,  H01L33/04 ,  H01L33/32 ,  H01L33/40 ,  H05B33/0803 ,  H05B33/0845

摘要： A light emitting diode (LED) to emit ultraviolet (UV) light includes a first n-type semiconductor region and a first p-type semiconductor region. The LED also includes an active region disposed between the first n-type semiconductor region and the first p-type semiconductor region, and in response to a bias applied across the light emitting diode, the active region emits UV light. A tunnel junction is disposed in the LED so the first p-type semiconductor region is disposed between the active region and the tunnel junction. The tunnel junction is electrically coupled to inject charge carriers into the active region through the first p-type semiconductor region. A second n-type semiconductor region is also disposed in the LED so the tunnel junction is disposed between the second n-type semiconductor region and the first p-type semiconductor region.

公开(公告)号：US20180040743A1

公开(公告)日：2018-02-08

申请号：US15670266

申请日：2017-08-07

申请人： ATOMERA INCORPORATED

发明人： ROBERT J. MEARS ,  Hideki Takeuchi ,  Marek Hytha

IPC分类号： H01L29/88 ,  H01L29/861 ,  H01L29/66 ,  H01L29/15

CPC分类号： H01L29/7376 ,  H01L27/092 ,  H01L29/1054 ,  H01L29/152 ,  H01L29/155 ,  H01L29/157 ,  H01L29/161 ,  H01L29/36 ,  H01L29/66007 ,  H01L29/6603 ,  H01L29/66121 ,  H01L29/66151 ,  H01L29/66477 ,  H01L29/66545 ,  H01L29/66651 ,  H01L29/78 ,  H01L29/7842 ,  H01L29/8618 ,  H01L29/882

摘要： A semiconductor device including at least one double-barrier resonant tunneling diode (DBRTD) is provided. The at least one DBRTD may include a first doped semiconductor layer, and a first barrier layer on the first doped semiconductor layer and including a superlattice. The DBRTD may further include a first intrinsic semiconductor layer on the first barrier layer, a second barrier layer on the first intrinsic semiconductor layer and also including the superlattice, a second intrinsic semiconductor layer on the second barrier layer, a third barrier layer on the second intrinsic semiconductor layer and also including the superlattice. A third intrinsic semiconductor layer may be on the third barrier layer, a fourth barrier layer may be on the third intrinsic semiconductor layer and also including the superlattice, a second doped semiconductor layer on the fourth barrier layer.

公开(公告)号：US09882019B2

公开(公告)日：2018-01-30

申请号：US15245468

申请日：2016-08-24

申请人： Qorvo US, Inc.

发明人： Peter V. Wright

IPC分类号： H01L29/93 ,  H01L29/66 ,  H01L29/861 ,  H01L27/08

CPC分类号： H01L29/66174 ,  H01L27/0808 ,  H01L29/6609 ,  H01L29/66121 ,  H01L29/66128 ,  H01L29/861 ,  H01L29/93

摘要： The present disclosure provides a method for fabricating a compound varactor. The method includes steps of depositing a collector layer, depositing a first base layer arranged in a first plurality of parallel fingers directly onto the collector layer, and depositing a second base layer arranged in a second plurality of parallel fingers that are interleaved with the first plurality of parallel fingers directly onto the collector layer.

公开(公告)号：US09865748B2

公开(公告)日：2018-01-09

申请号：US15488325

申请日：2017-04-14

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Hsin-Chih Chiang ,  Tung-Yang Lin ,  Chih-Chang Cheng ,  Ruey-Hsin Liu

IPC分类号： H01L29/68 ,  H01L29/87 ,  H01L29/66 ,  H01L29/06

CPC分类号： H01L29/87 ,  H01L29/0607 ,  H01L29/66121

摘要： A semiconductor structure includes a semiconductor substrate having a first electrical portion, a second electrical portion, and a bridged conductive layer. The first electrical portion includes a first semiconductor well, a second semiconductor well in the first semiconductor well, and a third semiconductor well and a fourth semiconductor well in the second semiconductor well. The second electrical portion includes a fifth semiconductor well, a semiconductor layer in the fifth semiconductor well, and a sixth semiconductor well and a seventh semiconductor well in the fifth semiconductor well. The semiconductor layer has separated first and second portions. The bridged conductive layer connects the fourth semiconductor well and the sixth semiconductor well.

公开(公告)号：US09711634B2

公开(公告)日：2017-07-18

申请号：US14882423

申请日：2015-10-13

申请人： FUJI ELECTRIC CO., LTD.

发明人： Takahiro Tamura ,  Yasuhiko Onishi

IPC分类号： H01L29/78 ,  H01L21/263 ,  H01L29/868 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66 ,  H01L29/739

CPC分类号： H01L29/66666 ,  H01L21/263 ,  H01L21/265 ,  H01L29/06 ,  H01L29/0634 ,  H01L29/0638 ,  H01L29/0688 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/1095 ,  H01L29/32 ,  H01L29/66121 ,  H01L29/66333 ,  H01L29/66712 ,  H01L29/7395 ,  H01L29/7803 ,  H01L29/7811 ,  H01L29/868

摘要： A super junction MOSFET includes a parallel pn layer including a plurality of pn junctions and in which an n-type drift region and a p-type partition region interposed between the pn junctions are alternately arranged and contact each other, a MOS gate structure on the surface of the parallel pn layer, and an n-type buffer layer in contact with an opposite main surface. The impurity concentration of the buffer layer is equal to or less than that of the n-type drift region. At least one of the p-type partition regions in the parallel pn layer is replaced with an n− region with a lower impurity concentration than the n-type drift region. With this structure, it is possible to provide a super junction MOSFET which prevents a sharp rise in hard recovery waveform during a reverse recovery operation.