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    Superjunction semiconductor device
    6.
    发明授权
    Superjunction semiconductor device 有权
    超结半导体器件

    公开(公告)号：US09123561B2

    公开(公告)日：2015-09-01

    申请号：US13657164

    申请日：2012-10-22

    Applicant: FUJI ELECTRIC CO., LTD.

    Inventor： Takahiro Tamura ,  Yasuhiko Onishi ,  Mutsumi Kitamura

    IPC: H01L29/66 ,  H01L29/08 ,  H01L29/78 ,  H01L29/06 ,  H01L29/40 ,  H01L29/10

    CPC classification number: H01L29/0878 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0638 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/7811

    Abstract: A superjunction semiconductor device is disclosed in which the trade-off relationship between breakdown voltage characteristics and voltage drop characteristics is considerably improved, and it is possible to greatly improve the charge resistance of an element peripheral portion and long-term breakdown voltage reliability. It includes parallel pn layers of n-type drift regions and p-type partition regions in superjunction structure. PN layers are depleted when off-state voltage is applied. Repeating pitch of the second parallel pn layer in a ring-like element peripheral portion encircling the element active portion is smaller than repeating pitch of the first parallel pn layer in the element active portion. Element peripheral portion includes low concentration n-type region on the surface of the second parallel pn layer. The depth of p-type partition region of an outer peripheral portion in the element peripheral portion is smaller than the depth of p-type partition region of an inner peripheral portion.

    Abstract translation: 公开了一种超级结半导体器件，其中击穿电压特性和电压降特性之间的折衷关系得到显着改善，并且可以大大提高元件周边部分的充电电阻和长期击穿电压可靠性。 它包括n型漂移区的并行pn层和超结构结构中的p型分区。 当施加截止电压时，PN层被耗尽。 围绕元件活性部分的环状元件周边部分中的第二平行pn层的重复间距小于元件活性部分中第一平行pn层的重复间距。 元件周边部分包括在第二平行pn层的表面上的低浓度n型区域。 元件周边部分的外周部分的p型分隔区域的深度小于内周部分的p型分隔区域的深度。

    Semiconductor device and fabrication method
    7.
    发明授权
    Semiconductor device and fabrication method 有权

    公开(公告)号：US11854782B2

    公开(公告)日：2023-12-26

    申请号：US17847170

    申请日：2022-06-23

    Applicant: FUJI ELECTRIC CO., LTD.

    Inventor： Yasunori Agata ,  Takahiro Tamura ,  Toru Ajiki

    IPC: H01L21/00 ,  H01L21/22 ,  H01L21/265 ,  H01L27/06 ,  H01L29/32 ,  H01L29/739 ,  H01L29/861 ,  H01L29/36

    CPC classification number: H01L21/221 ,  H01L21/26526 ,  H01L27/0664 ,  H01L29/32 ,  H01L29/36 ,  H01L29/7397 ,  H01L29/8613

    Abstract: A semiconductor device comprising a semiconductor substrate having upper and lower surfaces and a hydrogen containing region containing hydrogen and helium is provided. The carrier concentration distribution of the hydrogen containing region has: a first local maximum point; a second local maximum point closest to the first local maximum point among local maximum points positioned between the first local maximum point and the upper surface; a first intermediate point of the local minimum between the first and second local maximum points; and a second intermediate point closest to the second local maximum point among local minimum points or flat points where the carrier concentration remains constant positioned between the second local maximum point and the upper surface. A highest point of a helium concentration peak is positioned between the first and second local maximum points. The carrier concentration is lower at the first intermediate point than the second intermediate point.

    Semiconductor device
    8.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US11569092B2

    公开(公告)日：2023-01-31

    申请号：US17455664

    申请日：2021-11-18

    Applicant: FUJI ELECTRIC CO., LTD.

    Inventor： Takahiro Tamura ,  Yuichi Onozawa ,  Misaki Takahashi

    IPC: H01L21/22 ,  H01L27/06 ,  H01L29/32 ,  H01L29/868 ,  H01L21/322 ,  H01L29/861 ,  H01L21/265 ,  H01L27/07 ,  H01L29/36 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L29/08 ,  H01L29/10 ,  H01L29/739

    Abstract: A semiconductor device is provided. The semiconductor device includes: a first region formed on a front surface side of a semiconductor substrate; a drift region formed closer to a rear surface of the semiconductor substrate than the first region is; a buffer region that: is formed closer to the rear surface of the semiconductor substrate than the drift region is; and has one or more peaks of an impurity concentration that are higher than an impurity concentration of the drift region; and a lifetime killer that: is arranged on a rear surface side of the semiconductor substrate; and shortens a carrier lifetime, wherein a peak of a concentration of the lifetime killer is arranged between: a peak that is closest to a front surface of the semiconductor substrate among the peaks of the impurity concentration in the buffer region; and the rear surface of the semiconductor substrate.

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