公开(公告)号：US12205993B2

公开(公告)日：2025-01-21

申请号：US18310554

申请日：2023-05-02

Applicant: FUJI ELECTRIC CO., LTD.

Inventor： Hiroki Wakimoto ,  Hiroshi Takishita ,  Takashi Yoshimura ,  Takahiro Tamura ,  Yuichi Onozawa

IPC: H01L29/36 ,  H01L21/22 ,  H01L21/265 ,  H01L21/324 ,  H01L29/06 ,  H01L29/32 ,  H01L29/66 ,  H01L29/739 ,  H01L29/861 ,  H01L27/06

Abstract: A p-type semiconductor region is formed in a front surface side of an n-type semiconductor substrate. An n-type field stop (FS) region including protons as a donor is formed in a rear surface side of the semiconductor substrate. A concentration distribution of the donors in the FS region include first, second, third and fourth peaks in order from a front surface to the rear surface. Each of the peaks has a peak maximum point, and peak end points formed at both sides of the peak maximum point. The peak maximum points of the first and second peaks are higher than the peak maximum point of the third peak. The peak maximum point of the third peak is lower than the peak maximum point of the fourth peak.

公开(公告)号：US09608073B2

公开(公告)日：2017-03-28

申请号：US14932889

申请日：2015-11-04

Applicant: FUJI ELECTRIC CO., LTD.

Inventor： Toru Muramatsu ,  Hiroki Wakimoto

IPC: H01L29/08 ,  H01L29/66 ,  H01L29/73 ,  H01L29/10 ,  H01L29/739 ,  H03K17/567

CPC classification number: H01L29/1095 ,  H01L29/0834 ,  H01L29/66333 ,  H01L29/7393 ,  H01L29/7395 ,  H03K17/567

Abstract: Provided is a semiconductor device comprising: a first conductivity type base layer having a MOS gate structure formed on its front surface side; a second conductivity type first collector layer formed on a rear surface side of the base layer; a second conductivity type second collector layer formed on a rear surface side of the first collector layer with a material the same with that of the base layer, the second collector layer formed to be thinner than the first collector layer and having a higher impurity concentration than that of the first collector layer; a collector electrode formed on a rear surface side of the second collector layer; and a second conductivity type separation layer surrounding the MOS gate structure on a front surface side of the base layer and formed from a front surface of the base layer to a front surface of the first collector layer.

公开(公告)号：US08722487B2

公开(公告)日：2014-05-13

申请号：US13674630

申请日：2012-11-12

Applicant: Fuji Electric Co., Ltd.

Inventor： Kenichi Kazama ,  Tsunehiro Nakajima ,  Koji Sasaki ,  Akio Shimizu ,  Takashi Hayashi ,  Hiroki Wakimoto

IPC: H01L21/8249

CPC classification number: H01L29/7393 ,  H01L29/0834 ,  H01L29/41725 ,  H01L29/456 ,  H01L29/66333 ,  H01L29/7395

Abstract: A semiconductor device, including a silicon substrate having a first major surface and a second major surface, a front surface device structure formed in a region of the first major surface, and a rear electrode formed in a region of the second major surface. The rear electrode includes, as a first layer thereof, an aluminum silicon film that is formed by evaporating or sputtering aluminum-silicon onto the second major surface, the aluminum silicon film having a silicon concentration of at least 2 percent by weight and a thickness of less than 0.3 μm.

Abstract translation: 一种半导体器件，包括具有第一主表面和第二主表面的硅衬底，形成在第一主表面的区域中的前表面器件结构和形成在第二主表面的区域中的后电极。 后电极包括通过将铝硅蒸发或溅射到第二主表面上而形成的铝硅膜，所述铝硅膜的硅浓度至少为2重量％，厚度为 小于0.3μm。

公开(公告)号：US10923570B2

公开(公告)日：2021-02-16

申请号：US16430444

申请日：2019-06-04

Applicant: FUJI ELECTRIC CO., LTD.

Inventor： Hiroki Wakimoto ,  Hiroshi Takishita ,  Takashi Yoshimura ,  Takahiro Tamura ,  Yuichi Onozawa

IPC: H01L29/36 ,  H01L29/66 ,  H01L29/32 ,  H01L29/861 ,  H01L21/22 ,  H01L21/265 ,  H01L21/324 ,  H01L29/06 ,  H01L29/739 ,  H01L27/06

Abstract: A semiconductor device comprises: an n-type semiconductor substrate; a p-type anode region formed in the semiconductor substrate on its front surface side; an n-type field stop region formed in the semiconductor substrate on its rear surface side with protons as a donor; and an n-type cathode region formed in the semiconductor substrate to be closer to its rear surface than the field stop region is, wherein a concentration distribution of the donor in the field stop region in its depth direction has a first peak, and a second peak that is closer to the rear surface of the semiconductor substrate than the first peak is, and has a concentration lower than that of the first peak, and a carrier lifetime in at least a partial region between the anode region and the cathode region is longer than carrier lifetimes in the anode region.

公开(公告)号：US10388723B2

公开(公告)日：2019-08-20

申请号：US15791440

申请日：2017-10-24

Applicant: FUJI ELECTRIC CO., LTD.

Inventor： Hiroki Wakimoto ,  Yuichi Onozawa ,  Takahiro Tamura ,  Eri Ogawa

IPC: H01L29/06 ,  H01L29/861 ,  H01L21/265 ,  H01L21/324 ,  H01L29/66 ,  H01L29/32 ,  H01L29/36 ,  H01L29/87 ,  H01L29/167

Abstract: To prevent an intermediate region from contacting a cathode electrode even if a cathode region is partially defective. There is provided a semiconductor device with a semiconductor substrate that has a field stop region where first impurities of a first conduction type are implanted, an intermediate region that is formed on a back surface side of the field stop region and where second impurities of a second conduction type are implanted, and a cathode region of the first conduction type that is formed on a back surface side of the intermediate region. In a back surface of the semiconductor substrate, a concentration of the first impurities is higher than a concentration of the second impurities.

公开(公告)号：US09355858B2

公开(公告)日：2016-05-31

申请号：US14096477

申请日：2013-12-04

Applicant: FUJI ELECTRIC CO., LTD.

Inventor： Hiroki Wakimoto ,  Kenichi Iguchi ,  Koh Yoshikawa ,  Tsunehiro Nakajima ,  Shunsuke Tanaka ,  Masaaki Ogino

IPC: H01L21/00 ,  H01L21/308 ,  H01L21/78 ,  H01L21/302 ,  H01L29/06

CPC classification number: H01L21/308 ,  H01L21/302 ,  H01L21/78 ,  H01L29/06

Abstract: Some embodiments of the present invention relate to a semiconductor device and a method of manufacturing a semiconductor device capable of preventing the deterioration of electrical characteristics. A p-type collector region is provided on a surface layer of a backside surface of an n-type drift region. A p+-type isolation layer for obtaining reverse blocking capability is provided at the end of an element. In addition, a concave portion is provided so as to extend from the backside surface of the n-type drift region to the p+-type isolation layer. A p-type region is provided and is electrically connected to the p+-type isolation layer. The p+-type isolation layer is provided so as to include a cleavage plane having the boundary between the bottom and the side wall of the concave portion as one side.

Abstract translation: 本发明的一些实施例涉及能够防止电特性劣化的半导体器件和半导体器件的制造方法。 p型集电极区域设置在n型漂移区域的背面的表面层上。 在元件的末端提供了用于获得反向阻挡能力的p +型隔离层。 此外，设置从n型漂移区的背面向p +型隔离层延伸的凹部。 提供p型区域并且电连接到p +型隔离层。 提供p +型隔离层，以便包括具有作为一侧的凹部的底部和侧壁之间的边界的解理面。

公开(公告)号：US09793343B2

公开(公告)日：2017-10-17

申请号：US15257853

申请日：2016-09-06

Applicant: FUJI ELECTRIC CO., LTD.

Inventor： Eri Ogawa ,  Hiroki Wakimoto ,  Misaki Takahashi ,  Yuichi Onozawa

IPC: H01L29/94 ,  H01L29/06 ,  H01L29/08 ,  H01L29/40 ,  H01L29/739 ,  H01L29/78 ,  H01L29/10

CPC classification number: H01L29/0615 ,  H01L29/0619 ,  H01L29/08 ,  H01L29/0834 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/7397 ,  H01L29/7805 ,  H01L29/7811

Abstract: To improve withstand capability of a semiconductor device during reverse recovery, provided is a semiconductor device including a semiconductor substrate having a first conduction type; a first region having a second conduction type that is formed in a front surface of the semiconductor substrate; a second region having a second conduction type that is formed adjacent to the first region in the front surface of the semiconductor substrate and has a higher concentration than the first region; a third region having a second conduction type that is formed adjacent to the second region in the front surface of the semiconductor substrate and has a higher concentration than the second region; an insulating film that covers a portion of the second region and the third region; and an electrode connected to the second region and the first region that are not covered by the insulating film.

公开(公告)号：US09385210B2

公开(公告)日：2016-07-05

申请号：US14537279

申请日：2014-11-10

Applicant: FUJI ELECTRIC CO., LTD.

Inventor： Hiroki Wakimoto

IPC: H01L29/66 ,  H01L21/322 ,  H01L29/78 ,  H01L29/40 ,  H01L29/739 ,  H01L29/06 ,  H01L21/02

CPC classification number: H01L29/66333 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/0262 ,  H01L21/3221 ,  H01L29/0619 ,  H01L29/0646 ,  H01L29/404 ,  H01L29/7395 ,  H01L29/78

Abstract: In a method for manufacturing a reverse blocking MOS semiconductor device, a gettering polysilicon layer is formed on a rear surface of an FZ silicon substrate. Then, a p+ isolation layer for obtaining a reverse voltage blocking capability is formed. A front surface structure including a MOS gate structure is formed on a front surface of the FZ silicon substrate. The rear surface of the FZ silicon substrate is ground to reduce the thickness of the FZ silicon substrate. The gettering polysilicon layer is formed with such a thickness that it remains, without being vanished by single crystallization, until a process for forming the front surface structure including the MOS gate structure ends. Therefore, it is possible to sufficiently maintain the gettering function of the gettering polysilicon layer even in a heat treatment process subsequent to an isolation diffusion process.

Abstract translation: 在制造反向阻挡MOS半导体器件的方法中，在FZ硅衬底的后表面上形成吸杂多晶硅层。 然后，形成用于获得反向电压阻挡能力的p +隔离层。 在FZ硅衬底的前表面上形成包括MOS栅极结构的前表面结构。 研磨FZ硅衬底的后表面以减小FZ硅衬底的厚度。 吸气多晶硅层形成的厚度保持不变，直到用于形成包括MOS栅极结构的前表面结构的工艺结束为止，通过单一结晶消失。 因此，即使在隔离扩散处理之后的热处理工序中，也可以充分地保持吸杂多晶硅层的吸杂功能。

公开(公告)号：US11646350B2

公开(公告)日：2023-05-09

申请号：US17168124

申请日：2021-02-04

Applicant: FUJI ELECTRIC CO., LTD.

Inventor： Hiroki Wakimoto ,  Hiroshi Takishita ,  Takashi Yoshimura ,  Takahiro Tamura ,  Yuichi Onozawa

IPC: H01L29/36 ,  H01L29/66 ,  H01L29/32 ,  H01L29/861 ,  H01L21/22 ,  H01L21/265 ,  H01L21/324 ,  H01L29/06 ,  H01L29/739 ,  H01L27/06

CPC classification number: H01L29/36 ,  H01L21/221 ,  H01L21/265 ,  H01L21/324 ,  H01L29/0638 ,  H01L29/32 ,  H01L29/6609 ,  H01L29/66128 ,  H01L29/66348 ,  H01L29/7397 ,  H01L29/861 ,  H01L29/8611 ,  H01L21/26506 ,  H01L27/0664 ,  H01L29/0619

Abstract: A p-type semiconductor region is formed in a front surface side of an n-type semiconductor substrate. An n-type field stop (FS) region including protons as a donor is formed in a rear surface side of the semiconductor substrate. A concentration distribution of the donors in the FS region include first, second, third and fourth peaks in order from a front surface to the rear surface. Each of the peaks has a peak maximum point, and peak end points formed at both sides of the peak maximum point. The peak maximum points of the first and second peaks are higher than the peak maximum point of the third peak. The peak maximum point of the third peak is lower than the peak maximum point of the fourth peak.

公开(公告)号：US10312331B2

公开(公告)日：2019-06-04

申请号：US15169740

申请日：2016-06-01

Applicant: FUJI ELECTRIC CO., LTD.

Inventor： Hiroki Wakimoto ,  Hiroshi Takishita ,  Takashi Yoshimura ,  Takahiro Tamura ,  Yuichi Onozawa

IPC: H01L21/22 ,  H01L27/06 ,  H01L29/06 ,  H01L29/32 ,  H01L29/36 ,  H01L29/66 ,  H01L21/265 ,  H01L21/324 ,  H01L29/739 ,  H01L29/861

Abstract: A semiconductor device comprises: an n-type semiconductor substrate; a p-type anode region formed in the semiconductor substrate on its front surface side; an n-type field stop region formed in the semiconductor substrate on its rear surface side with protons as a donor; and an n-type cathode region formed in the semiconductor substrate to be closer to its rear surface than the field stop region is, wherein a concentration distribution of the donor in the field stop region in its depth direction has a first peak, and a second peak that is closer to the rear surface of the semiconductor substrate than the first peak is, and has a concentration lower than that of the first peak, and a carrier lifetime in at least a partial region between the anode region and the cathode region is longer than carrier lifetimes in the anode region.