公开(公告)号：US20240332432A1

公开(公告)日：2024-10-03

申请号：US18194303

申请日：2023-03-31

申请人： Intel Corporation

发明人： Sukru Yemenicioglu ,  Abhishek Anil Sharma ,  Sudipto Naskar ,  Kalyan C. Kolluru

IPC分类号： H01L29/93 ,  H01L29/417 ,  H01L29/66

CPC分类号： H01L29/93 ,  H01L29/417 ,  H01L29/66022 ,  H01L29/66196 ,  H01L29/66969 ,  H01L29/2003 ,  H01L29/24

摘要： An integrated circuit device comprising a varactor comprising a first conductive contact; a second conductive contact; and a thin film transistor (TFT) channel material coupled between the first conductive contact and the second conductive contact.

公开(公告)号：US20240222369A1

公开(公告)日：2024-07-04

申请号：US18098710

申请日：2023-01-19

申请人： UNITED MICROELECTRONICS CORP.

发明人： Ching-Wen Hung ,  Peng-Hsiu Chen ,  Su-Ming Hsieh ,  Ying-Ren Chen

IPC分类号： H01L27/08 ,  H01L29/66 ,  H01L29/93

CPC分类号： H01L27/0808 ,  H01L29/66174 ,  H01L29/93

摘要： The invention provides a layout pattern of a semiconductor varactor, which comprises a plurality of varactor units arranged on a substrate, wherein each varactor unit comprises a plurality of fin structures arranged in parallel with each other, a plurality of gate structures arranged in parallel with each other, located on the substrate and spanning the fin structures, and a gate metal layer electrically connected with the plurality of gate structures.

公开(公告)号：US12015027B2

公开(公告)日：2024-06-18

申请号：US17851047

申请日：2022-06-28

申请人： Innolux Corporation

发明人： Tang Chin Hung ,  Chin-Lung Ting ,  Chung-Kuang Wei ,  Ker-Yih Kao ,  Tong-Jung Wang ,  Chih-Yung Hsieh ,  Hao Jung Huang ,  I-Yin Li ,  Chia-Chi Ho ,  Yi Hung Lin ,  Cheng-Hsu Chou ,  Chia-Ping Tseng

IPC分类号： H01L27/06 ,  H01L21/8234 ,  H01L23/522 ,  H01L29/93 ,  H01L23/538

CPC分类号： H01L27/0629 ,  H01L21/823475 ,  H01L23/5223 ,  H01L29/93 ,  H01L23/5385 ,  H01L27/0694

摘要： The disclosure provides an electromagnetic wave adjustment apparatus includes a control circuit, a transistor circuit die and an electronic assembly. The transistor circuit die receives a control signal from the control circuit and drives the electronic assembly.

公开(公告)号：US20240177937A1

公开(公告)日：2024-05-30

申请号：US18176492

申请日：2023-03-01

申请人： YAGEO CORPORATION

发明人： Masayuki FUJIMOTO ,  Kai-Hsun YANG ,  I Kuan CHENG

IPC分类号： H01G4/30 ,  H01G4/008 ,  H01G4/012 ,  H01G4/12 ,  H01G4/232 ,  H01G4/248 ,  H01G13/00 ,  H01L29/66 ,  H01L29/93

CPC分类号： H01G4/306 ,  H01G4/008 ,  H01G4/012 ,  H01G4/1272 ,  H01G4/232 ,  H01G4/248 ,  H01G13/006 ,  H01L29/66174 ,  H01L29/93

摘要： The present application relates to a multi-layer ceramic capacitor and a method for producing the same. Internal electrode layers and ceramic dielectric layers are firstly formed, and the internal electrode layers and the ceramic dielectric layers are alternately laminated to form a laminated stack. The internal electrode layers are formed from specific metal particles. Next, a sintering process is performed to the laminated stack to form a laminated ceramic body, and then end electrodes are formed on two ends of the laminated ceramic body, thereby producing the multi-layer ceramic capacitor of the present application with excellent continuity of the internal electrode and better capacitor properties and reliability.

公开(公告)号：US11978810B2

公开(公告)日：2024-05-07

申请号：US17324402

申请日：2021-05-19

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Liang-Yu Su ,  Chih-Wen Yao ,  Hsiao-Chin Tuan ,  Ming-Ta Lei

IPC分类号： H01L29/66 ,  H01L27/08 ,  H01L29/06 ,  H01L29/93

CPC分类号： H01L29/93 ,  H01L27/0808 ,  H01L29/063 ,  H01L29/66174

摘要： Various embodiments of the present disclosure are directed towards a method for forming a varactor comprising a reduced surface field (RESURF) region. The method includes forming a drift region having a first doping type within a substrate. A RESURF region having a second doping type is formed within the substrate such that the RESURF region is below the drift region. A gate structure is formed on the substrate. A pair of contact regions is formed within the substrate on opposing sides of the gate structure. The contact regions respectively abut the drift region and have the first doping type, and wherein the first doping type is opposite the second doping type.

公开(公告)号：US11961836B2

公开(公告)日：2024-04-16

申请号：US16147205

申请日：2018-09-28

申请人： Intel Corporation

发明人： Hyung-Jin Lee ,  Mark Armstrong ,  Saurabh Morarka ,  Carlos Nieva-Lozano ,  Ayan Kar

IPC分类号： H01L27/08 ,  H01L29/66 ,  H01L29/93 ,  H10B99/00

CPC分类号： H01L27/0808 ,  H01L29/66174 ,  H01L29/93 ,  H10B99/00

摘要： An integrated circuit structure comprises one or more fins extending above a surface of a substrate over an N-type well. A gate is over and in contact with the one or more fins. A second shallow N-type doping is below the gate and above the N-type well.

公开(公告)号：US20230341345A1

公开(公告)日：2023-10-26

申请号：US18068600

申请日：2022-12-20

申请人： Regents of the University of Minnesota

发明人： Steven J. Koester

IPC分类号： G01N27/22 ,  H01L29/10 ,  H01L29/16 ,  H01L29/423 ,  H01L29/93 ,  H01L31/08 ,  H01L31/115 ,  G01R27/26

CPC分类号： G01N27/221 ,  G01N27/227 ,  H01L29/1025 ,  H01L29/1606 ,  H01L29/42312 ,  H01L29/93 ,  H01L31/085 ,  H01L31/115 ,  G01R27/2605

摘要： An electrical device includes at least one graphene quantum capacitance varactor. In some examples, the graphene quantum capacitance varactor includes an insulator layer, a graphene layer disposed on the insulator layer, a dielectric layer disposed on the graphene layer, a gate electrode formed on the dielectric layer, and at least one contact electrode disposed on the graphene layer and making electrical contact with the graphene layer. In other examples, the graphene quantum capacitance varactor includes an insulator layer, a gate electrode recessed in the insulator layer, a dielectric layer formed on the gate electrode, a graphene layer formed on the dielectric layer, wherein the graphene layer comprises an exposed surface opposite the dielectric layer, and at least one contact electrode formed on the graphene layer and making electrical contact with the graphene layer.

公开(公告)号：US20230187435A1

公开(公告)日：2023-06-15

申请号：US17988038

申请日：2022-11-16

申请人： SKYWORKS SOLUTIONS, INC.

发明人： Min-Zing Tseng ,  Renfeng Jin

IPC分类号： H01L27/02 ,  H02H9/02 ,  H01L29/93

CPC分类号： H01L27/0255 ,  H01L29/93 ,  H02H9/02

摘要： A semiconductor device and a corresponding circuit for shunting current in a circuit protection configuration is disclosed. An example device includes a first semiconductor region having an anode electrical contact, a second semiconductor region having a cathode electrical contact, a third semiconductor region extending between the first semiconductor region and the second semiconductor region, the second semiconductor region and the third semiconductor region forming a PN junction therebetween, and a gate coupled to the third semiconductor region. The gate is controllable between a first mode in which additional space charges are induced in the semiconductor region to deplete the semiconductor region, and a second mode in which additional space charges are not induced in the semiconductor region.

公开(公告)号：US11569393B2

公开(公告)日：2023-01-31

申请号：US16813702

申请日：2020-03-09

申请人： Futurewei Technologies, Inc.

发明人： Brian Creed ,  Lawrence E. Connell ,  Kent Jaeger ,  Matthew Richard Miller

IPC分类号： H01L27/08 ,  H01L29/10 ,  H01L29/94 ,  H01L29/93 ,  H01L29/66

摘要： Embodiments are provided herein for low loss coupling capacitor structures. The embodiments include a n-type varactor (NVAR) configuration and p-type varactor (PVAR) configuration. The structure in the NVAR configuration comprises a p-doped semiconductor substrate (Psub), a deep n-doped semiconductor well (DNW) in the Psub, and a p-doped semiconductor well (P well) in the DNW. The circuit structure further comprises a source terminal of a p-doped semiconductor material within P well, and a drain terminal of the p-doped semiconductor material within the P well. Additionally, the circuit structure comprises an insulated gate on the surface of the P well, a metal pattern comprising a plurality of layers of metal lines, and a plurality of vias through the metal lines. The vias are contacts connecting the metal lines to the gate, the source terminal, and the drain terminal.

公开(公告)号：US11561192B2

公开(公告)日：2023-01-24

申请号：US17249213

申请日：2021-02-24

申请人： Regents of the University of Minnesota

发明人： Steven J. Koester

IPC分类号： H01L29/93 ,  G01N27/22 ,  H01L29/10 ,  H01L29/16 ,  H01L29/423 ,  H01L31/08 ,  H01L31/115 ,  G01R27/26

摘要： An electrical device includes at least one graphene quantum capacitance varactor. In some examples, the graphene quantum capacitance varactor includes an insulator layer, a graphene layer disposed on the insulator layer, a dielectric layer disposed on the graphene layer, a gate electrode formed on the dielectric layer, and at least one contact electrode disposed on the graphene layer and making electrical contact with the graphene layer. In other examples, the graphene quantum capacitance varactor includes an insulator layer, a gate electrode recessed in the insulator layer, a dielectric layer formed on the gate electrode, a graphene layer formed on the dielectric layer, wherein the graphene layer comprises an exposed surface opposite the dielectric layer, and at least one contact electrode formed on the graphene layer and making electrical contact with the graphene layer.