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公开(公告)号：US20230411326A1
公开(公告)日：2023-12-21
申请号：US17841686
申请日：2022-06-16
发明人： Chen-Yu Tsai , Ku-Feng Yang , Tsang-Jiuh Wu , Wen-Chih Chiou
IPC分类号： H01L23/00
CPC分类号： H01L24/08 , H01L24/80 , H01L2224/08111 , H01L2224/08145 , H01L2224/80895 , H01L2224/80896
摘要： A semiconductor structure including a first die, a second die stacked on the first die, a smoothing layer disposed on the first die and a filling material layer disposed on the smoothing layer. The second die has a dielectric portion and a semiconductor material portion disposed on the dielectric portion. The smoothing layer includes a first dielectric layer and a second dielectric layer, and the second dielectric layer is disposed on the first dielectric layer. The dielectric portion is surrounded by the smoothing layer, and the semiconductor material portion is surrounded by the filling material layer. A material of the first dielectric layer is different from a material of the second dielectric layer and a material of the filling material layer.
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公开(公告)号：US11487060B2
公开(公告)日：2022-11-01
申请号：US17213198
申请日：2021-03-25
发明人： Yu-Kuang Liao , Jia-Xsing Li , Ping-Jung Wu , Tsang-Jiuh Wu , Wen-Chih Chiou , Chen-Hua Yu
摘要： A semiconductor device includes a photonic die and an optical die. The photonic die includes a grating coupler and an optical device. The optical device is connected to the grating coupler to receive radiation of predetermined wavelength incident on the grating coupler. The optical die is disposed over the photonic die and includes a substrate with optical nanostructures. Positions and shapes of the optical nanostructures are such to perform an optical transformation on the incident radiation of predetermined wavelength when the incident radiation passes through an area of the substrate where the optical nanostructures are located. The optical nanostructures overlie the grating coupler so that the incident radiation of predetermined wavelength crosses the optical die where the optical nanostructures are located before reaching the grating coupler.
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公开(公告)号：US10784162B2
公开(公告)日：2020-09-22
申请号：US16168306
申请日：2018-10-23
发明人： Chen-Hua Yu , Cheng-Hung Chang , Ebin Liao , Chia-Lin Yu , Hsiang-Yi Wang , Chun Hua Chang , Li-Hsien Huang , Darryl Kuo , Tsang-Jiuh Wu , Wen-Chih Chiou
IPC分类号： H01L21/768 , H01L23/48 , H01L23/498 , H01L21/02 , H01L21/306 , H01L21/3105 , H01L21/321 , H01L25/065 , H01L25/11 , H01L23/538 , H01L25/04 , H01L25/07 , H01L25/075
摘要： A method of making a semiconductor component includes etching a substrate to define an opening. The method further includes depositing a first dielectric liner in the opening, wherein the first dielectric liner has a first stress. The method further includes depositing a second dielectric liner over the first dielectric liner, wherein the second dielectric liner has a second stress, and a direction of the first stress is opposite a direction of the second stress. The method further includes depositing a conductive material over the second dielectric liner.
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公开(公告)号：US10510641B2
公开(公告)日：2019-12-17
申请号：US15269753
申请日：2016-09-19
发明人： Yung-Chi Lin , Hsin-Yu Chen , Ming-Tsu Chung , HsiaoYun Lo , Hong-Ye Shih , Chia-Yin Chen , Ku-Feng Yang , Tsang-Jiuh Wu , Wen-Chih Chiou
IPC分类号： H01L23/48 , H01L21/768
摘要： A semiconductor device includes a through-substrate via extending from a frontside to a backside of a semiconductor substrate. The through-substrate via includes a concave or a convex portion adjacent to the backside of the semiconductor substrate. An isolation film is formed on the backside of the semiconductor substrate. A conductive layer includes a first portion formed on the concave or convex portion of the through substrate via and a second portion formed on the isolation film. A passivation layer partially covers the conductive layer.
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公开(公告)号：US10290604B2
公开(公告)日：2019-05-14
申请号：US15837704
申请日：2017-12-11
发明人： Lin-Chih Huang , Hung-An Teng , Hsin-Yu Chen , Tsang-Jiuh Wu , Cheng-Chieh Hsieh
IPC分类号： H01L21/00 , H01L23/00 , H01L21/78 , H01L23/538 , H01L23/498 , H01L21/683 , H01L25/065 , H01L25/00 , H01L23/14 , H01L21/56 , H01L23/31
摘要： Integrated circuit packages and methods of forming the same are provided. One or more redistribution layers are formed on a carrier. First connectors are formed on a first side of the RDLs. Dies are bonded to the first side of the RDLs using the first connectors. An encapsulant is formed on the first side of the RDLs around the dies. The carrier is de-bonded from the overlaying structure and second connectors are formed on a second side of the RDLs. The resulting structure in diced to form individual packages.
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公开(公告)号：US20180350778A1
公开(公告)日：2018-12-06
申请号：US16046285
申请日：2018-07-26
发明人： Chen-Hua Yu , Tsang-Jiuh Wu , Wen-Chih Chiou
IPC分类号： H01L25/065 , H01L21/56 , H01L21/78 , H01L23/31 , H01L25/00
CPC分类号： H01L25/0657 , H01L21/561 , H01L21/568 , H01L21/78 , H01L23/3114 , H01L25/50 , H01L2224/11 , H01L2225/06513 , H01L2225/06527 , H01L2225/06541 , H01L2225/06548 , H01L2225/06555
摘要： Methods of singulation and bonding, as well as structures formed thereby, are disclosed. A method includes singulating a first chip and after the singulating the first chip, bonding the first chip to a second chip. The first chip includes a first semiconductor substrate and a first interconnect structure on a front side of the first semiconductor substrate. The singulating the first chip includes etching through a back side of the first semiconductor substrate through the first interconnect structure.
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公开(公告)号：US20180145046A1
公开(公告)日：2018-05-24
申请号：US15863240
申请日：2018-01-05
发明人： Hsiao Yun Lo , Lin-Chih Huang , Tasi-Jung Wu , Hsin-Yu Chen , Yung-Chi Lin , Ku-Feng Yang , Tsang-Jiuh Wu , Wen-Chih Chiou
IPC分类号： H01L23/00
摘要： A device includes a first side interconnect structure over a first side of a substrate, wherein active circuits are in the substrate and adjacent to the first side of the substrate, a dielectric layer over a second side of the substrate, a pad embedded in the dielectric layer, the pad comprising an upper portion and a bottom portion formed of two different materials and a passivation layer over the dielectric layer.
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公开(公告)号：US20180012825A1
公开(公告)日：2018-01-11
申请号：US15713011
申请日：2017-09-22
发明人： Ku-Feng Yang , Ming-Tsu Chung , Hong-Ye Shih , Jiung Wu , Chen-Yu Tsai , Hsin-Yu Chen , Tsang-Jiuh Wu , Wen-Chih Chiou
IPC分类号： H01L23/48 , H01L21/768 , H01L23/544 , H01L25/00 , H01L23/00 , H01L25/065
CPC分类号： H01L23/481 , H01L21/7684 , H01L21/76898 , H01L23/544 , H01L24/05 , H01L24/13 , H01L24/81 , H01L25/0657 , H01L25/50 , H01L2223/5442 , H01L2223/54426 , H01L2223/5446 , H01L2224/0401 , H01L2224/05009 , H01L2224/05022 , H01L2224/05124 , H01L2224/05147 , H01L2224/05155 , H01L2224/05166 , H01L2224/05171 , H01L2224/05571 , H01L2224/06181 , H01L2224/11 , H01L2224/1132 , H01L2224/11334 , H01L2224/1134 , H01L2224/1145 , H01L2224/11462 , H01L2224/13111 , H01L2224/13139 , H01L2224/13147 , H01L2224/16146 , H01L2224/17181 , H01L2224/2919 , H01L2224/29191 , H01L2224/32145 , H01L2224/73204 , H01L2224/81 , H01L2224/8113 , H01L2224/81132 , H01L2224/81815 , H01L2224/81895 , H01L2224/83104 , H01L2224/92125 , H01L2224/94 , H01L2225/06513 , H01L2225/06541 , H01L2225/06544 , H01L2225/06565 , H01L2225/06593 , H01L2924/00012 , H01L2924/01029 , H01L2924/01074 , H01L2924/3512 , H01L2924/014 , H01L2924/00014 , H01L2224/03
摘要： An apparatus comprising a substrate with multiple electronic devices. An interconnect structure formed on a first side of the substrate interconnects the electronic devices. Dummy TSVs each extend through the substrate and form an alignment mark on a second side of the substrate. Functional TSVs each extend through the substrate and electrically connect to the electronic devices. A redistribution layer (RDL) formed on the second side of the substrate interconnects ones of the dummy TSVs with ones of the functional TSVs. Step heights of the RDL over the functional TSVs are less than a predetermined value, whereas step heights of the RDL over the dummy TSVs are greater than the predetermined value.
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公开(公告)号：US09847256B2
公开(公告)日：2017-12-19
申请号：US15369409
申请日：2016-12-05
发明人： Yung-Chi Lin , Yen-Hung Chen , Yin-Hua Chen , Ebin Liao , Ku-Feng Yang , Tsang-Jiuh Wu , Wen-Chih Chiou
IPC分类号： H01L21/768 , H01L21/4763 , H01L23/532 , H01L23/48
CPC分类号： H01L21/76898 , H01L21/76849 , H01L23/481 , H01L23/53209 , H01L23/53223 , H01L23/53238 , H01L23/53252 , H01L23/53266 , H01L2924/0002 , H01L2924/00
摘要： A device including a first dielectric layer on a semiconductor substrate, a gate electrode formed in the first dielectric layer, and a through-substrate via (TSV) structure penetrating the first dielectric layer and extending into the semiconductor substrate. The TSV structure includes a conductive layer, a diffusion barrier layer surrounding the conductive layer and an isolation layer surrounding the diffusion barrier layer. A capping layer including cobalt is formed on the top surface of the conductive layer of the TSV structure.
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公开(公告)号：US20170148765A1
公开(公告)日：2017-05-25
申请号：US14950915
申请日：2015-11-24
发明人： Chen-Hua Yu , Tsang-Jiuh Wu , Wen-Chih Chiou
IPC分类号： H01L25/065 , H01L25/00 , H01L21/78
CPC分类号： H01L25/0657 , H01L21/561 , H01L21/568 , H01L21/76898 , H01L21/78 , H01L23/3114 , H01L25/50 , H01L2224/11 , H01L2225/06513 , H01L2225/06527 , H01L2225/06541 , H01L2225/06548 , H01L2225/06555
摘要： Methods of singulation and bonding, as well as structures formed thereby, are disclosed. A method includes singulating a first chip and after the singulating the first chip, bonding the first chip to a second chip. The first chip includes a first semiconductor substrate and a first interconnect structure on a front side of the first semiconductor substrate. The singulating the first chip includes etching through a back side of the first semiconductor substrate through the first interconnect structure.
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