公开(公告)号：US20150235940A1

公开(公告)日：2015-08-20

申请号：US14685023

申请日：2015-04-13

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hsin-Yu Chen ,  Ku-Feng Yang ,  Tasi-Jung Wu ,  Lin-Chih Huang ,  Yuan-Hung Liu ,  Tsang-Jiuh Wu ,  Wen-Chih Chiou

IPC: H01L23/528 ,  H01L27/06 ,  H01L23/538 ,  H01L23/522

CPC classification number: H01L23/528 ,  H01L21/76807 ,  H01L23/3114 ,  H01L23/3171 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5384 ,  H01L27/0617 ,  H01L2221/1031 ,  H01L2224/13 ,  H01L2924/13091 ,  H01L2924/00

Abstract: An apparatus comprises an interlayer dielectric layer formed on a first side of a substrate, a first photo-sensitive dielectric layer formed over the interlayer dielectric layer, wherein the first photo-sensitive dielectric layer comprises a first metal structure and a second photo-sensitive dielectric layer formed over the first photo-sensitive dielectric, wherein the second photo-sensitive dielectric layer comprises a second metal structure having a bottom surface coplanar with a top surface of the first metal structure.

Abstract translation: 一种装置包括形成在衬底的第一侧上的层间介质层，形成在层间电介质层上的第一光敏电介质层，其中第一光敏电介质层包括第一金属结构和第二光敏电介质 所述第二光敏电介质层包括具有与所述第一金属结构的顶表面共面的底表面的第二金属结构。

公开(公告)号：US20180145046A1

公开(公告)日：2018-05-24

申请号：US15863240

申请日：2018-01-05

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hsiao Yun Lo ,  Lin-Chih Huang ,  Tasi-Jung Wu ,  Hsin-Yu Chen ,  Yung-Chi Lin ,  Ku-Feng Yang ,  Tsang-Jiuh Wu ,  Wen-Chih Chiou

IPC: H01L23/00

Abstract: A device includes a first side interconnect structure over a first side of a substrate, wherein active circuits are in the substrate and adjacent to the first side of the substrate, a dielectric layer over a second side of the substrate, a pad embedded in the dielectric layer, the pad comprising an upper portion and a bottom portion formed of two different materials and a passivation layer over the dielectric layer.

公开(公告)号：US20150130058A1

公开(公告)日：2015-05-14

申请号：US14604294

申请日：2015-01-23

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hsin-Yu Chen ,  Lin-Chih Huang ,  Tsang-Jiuh Wu ,  Tasi-Jung Wu ,  Wen-Chih Chiou

IPC: H01L23/00 ,  H01L23/522 ,  H01L23/532 ,  H01L23/528

CPC classification number: H01L24/14 ,  H01L21/6835 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53238 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/96 ,  H01L25/0657 ,  H01L2221/68359 ,  H01L2221/68381 ,  H01L2224/11424 ,  H01L2224/11464 ,  H01L2224/13025 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/81005 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2224/96 ,  H01L2924/06 ,  H01L2924/07025 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/01047 ,  H01L2224/81

Abstract: Methods of making and an integrated circuit device. An embodiment method includes patterning a first polymer layer disposed over a first copper seed layer, electroplating a through polymer via in the first polymer layer using the first copper seed layer, a via end surface offset from a first polymer layer surface, forming a second polymer layer over the first polymer layer, the second polymer layer patterned to expose the via end surface, and electroplating an interconnect in the second polymer layer to cap the via end surface using a second copper seed layer.

Abstract translation: 制造方法和集成电路器件。 一种实施方式包括图案化设置在第一铜籽晶层上的第一聚合物层，使用第一铜种子层在第一聚合物层中电镀穿过聚合物通孔，从第一聚合物层表面偏移的通孔端表面，形成第二聚合物 在第一聚合物层上方形成第二聚合物层，第二聚合物层图案化以暴露通孔端面，以及在第二聚合物层中电镀互连以通过第二铜种子层覆盖通孔端面。

公开(公告)号：US09679859B2

公开(公告)日：2017-06-13

申请号：US14991560

申请日：2016-01-08

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hsiao Yun Lo ,  Lin-Chih Huang ,  Tasi-Jung Wu ,  Hsin-Yu Chen ,  Yung-Chi Lin ,  Ku-Feng Yang ,  Tsang-Jiuh Wu ,  Wen-Chih Chiou

IPC: H01L29/40 ,  H01L23/00

CPC classification number: H01L24/05 ,  H01L23/481 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/03462 ,  H01L2224/03602 ,  H01L2224/03614 ,  H01L2224/03616 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05012 ,  H01L2224/05017 ,  H01L2224/05025 ,  H01L2224/05026 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05187 ,  H01L2224/05565 ,  H01L2224/05571 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05684 ,  H01L2224/11334 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/13023 ,  H01L2224/13026 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/013 ,  H01L2924/13091 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/014

Abstract: An apparatus comprises a dielectric layer formed on a first side of a substrate, a first side interconnect structure comprising a first metal line and a pad formed in the dielectric layer, wherein the pad comprises a bottom portion formed of a first conductive metal and an upper portion formed of a second conductive metal, and wherein sidewalls of the upper portion are surrounded by the bottom portion and a top surface of the pad is coplanar with a top surface of the first metal line and a passivation layer formed over the dielectric layer.

公开(公告)号：US09252110B2

公开(公告)日：2016-02-02

申请号：US14158364

申请日：2014-01-17

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hsiao Yun Lo ,  Lin-Chih Huang ,  Tasi-Jung Wu ,  Hsin-Yu Chen ,  Yung-Chi Lin ,  Ku-Feng Yang ,  Tsang-Jiuh Wu ,  Wen-Chih Chiou

IPC: H01L21/4763 ,  H01L23/00

CPC classification number: H01L24/05 ,  H01L23/481 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/03462 ,  H01L2224/03602 ,  H01L2224/03614 ,  H01L2224/03616 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05012 ,  H01L2224/05017 ,  H01L2224/05025 ,  H01L2224/05026 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05187 ,  H01L2224/05565 ,  H01L2224/05571 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05684 ,  H01L2224/11334 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/13023 ,  H01L2224/13026 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/013 ,  H01L2924/13091 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/014

Abstract: An apparatus comprises a dielectric layer formed on a first side of a substrate, a first side interconnect structure comprising a first metal line and a pad formed in the dielectric layer, wherein the pad comprises a bottom portion formed of a first conductive metal and an upper portion formed of a second conductive metal, and wherein sidewalls of the upper portion are surrounded by the bottom portion and a top surface of the pad is coplanar with a top surface of the first metal line and a passivation layer formed over the dielectric layer, wherein the first metal line is embedded in the passivation layer.

Abstract translation: 一种装置包括形成在基板的第一侧上的电介质层，第一侧互连结构，包括第一金属线和形成在电介质层中的焊盘，其中该焊盘包括由第一导电金属和上部 部分由第二导电金属形成，并且其中上部的侧壁由底部包围，并且焊盘的顶表面与第一金属线的顶表面和形成在电介质层上的钝化层共面，其中 第一金属线嵌入在钝化层中。

公开(公告)号：US08951838B2

公开(公告)日：2015-02-10

申请号：US13830570

申请日：2013-03-14

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hsin-Yu Chen ,  Lin-Chih Huang ,  Tasi-Jung Wu ,  Tsang-Jiuh Wu ,  Wen-Chih Chiou

IPC: H01L21/44 ,  H01L23/00

CPC classification number: H01L24/14 ,  H01L21/6835 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53238 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/96 ,  H01L25/0657 ,  H01L2221/68359 ,  H01L2221/68381 ,  H01L2224/11424 ,  H01L2224/11464 ,  H01L2224/13025 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/81005 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2224/96 ,  H01L2924/06 ,  H01L2924/07025 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/01047 ,  H01L2224/81

Abstract: Methods of making and an integrated circuit device. An embodiment method includes patterning a first polymer layer disposed over a first copper seed layer, electroplating a through polymer via in the first polymer layer using the first copper seed layer, a via end surface offset from a first polymer layer surface, forming a second polymer layer over the first polymer layer, the second polymer layer patterned to expose the via end surface, and electroplating an interconnect in the second polymer layer to cap the via end surface using a second copper seed layer.

Abstract translation: 制造方法和集成电路器件。 一种实施方式包括图案化设置在第一铜籽晶层上的第一聚合物层，使用第一铜种子层在第一聚合物层中电镀穿过聚合物通孔，从第一聚合物层表面偏移的通孔端表面，形成第二聚合物 在第一聚合物层上方形成第二聚合物层，第二聚合物层图案化以暴露通孔端面，以及在第二聚合物层中电镀互连以通过第二铜种子层覆盖通孔端面。

公开(公告)号：US10811374B2

公开(公告)日：2020-10-20

申请号：US15863240

申请日：2018-01-05

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hsiao Yun Lo ,  Lin-Chih Huang ,  Tasi-Jung Wu ,  Hsin-Yu Chen ,  Yung-Chi Lin ,  Ku-Feng Yang ,  Tsang-Jiuh Wu ,  Wen-Chih Chiou

IPC: H01L23/00 ,  H01L23/48

Abstract: A device includes a first side interconnect structure over a first side of a substrate, wherein active circuits are in the substrate and adjacent to the first side of the substrate, a dielectric layer over a second side of the substrate, a pad embedded in the dielectric layer, the pad comprising an upper portion and a bottom portion formed of two different materials and a passivation layer over the dielectric layer.

公开(公告)号：US10157866B2

公开(公告)日：2018-12-18

申请号：US15613579

申请日：2017-06-05

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hsiao Yun Lo ,  Lin-Chih Huang ,  Tasi-Jung Wu ,  Hsin-Yu Chen ,  Yung-Chi Lin ,  Ku-Feng Yang ,  Tsang-Jiuh Wu ,  Wen-Chih Chiou

IPC: H01L21/44 ,  H01L23/00 ,  H01L23/48

Abstract: A method includes depositing a dielectric layer over a substrate, patterning the dielectric layer to form a first opening and a second opening, wherein a width of the second opening is greater than a width of the first opening, forming a first metal layer over the dielectric layer, wherein a planar surface of the first metal layer in the second opening is lower than a top surface of the dielectric layer, forming a second metal layer in a conformal manner over the first metal layer, wherein a material of the first metal layer is different from a material of the second metal layer and applying a polishing process to the first metal layer and the second metal layer until the dielectric layer is exposed.

公开(公告)号：US20150206846A1

公开(公告)日：2015-07-23

申请号：US14158364

申请日：2014-01-17

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hsiao Yun Lo ,  Lin-Chih Huang ,  Tasi-Jung Wu ,  Hsin-Yu Chen ,  Yung-Chi Lin ,  Ku-Feng Yang ,  Tsang-Jiuh Wu ,  Wen-Chih Chiou

IPC: H01L23/00

CPC classification number: H01L24/05 ,  H01L23/481 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/03462 ,  H01L2224/03602 ,  H01L2224/03614 ,  H01L2224/03616 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05012 ,  H01L2224/05017 ,  H01L2224/05025 ,  H01L2224/05026 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05187 ,  H01L2224/05565 ,  H01L2224/05571 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05684 ,  H01L2224/11334 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/13023 ,  H01L2224/13026 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/013 ,  H01L2924/13091 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/014

Abstract: An apparatus comprises a dielectric layer formed on a first side of a substrate, a first side interconnect structure comprising a first metal line and a pad formed in the dielectric layer, wherein the pad comprises a bottom portion formed of a first conductive metal and an upper portion formed of a second conductive metal, and wherein sidewalls of the upper portion are surrounded by the bottom portion and a top surface of the pad is coplanar with a top surface of the first metal line and a passivation layer formed over the dielectric layer, wherein the first metal line is embedded in the passivation layer.

Abstract translation: 一种装置包括形成在基板的第一侧上的电介质层，第一侧互连结构，包括第一金属线和形成在电介质层中的焊盘，其中该焊盘包括由第一导电金属和上部 部分由第二导电金属形成，并且其中上部的侧壁由底部包围，并且焊盘的顶表面与第一金属线的顶表面和形成在电介质层上的钝化层共面，其中 第一金属线嵌入在钝化层中。

公开(公告)号：US20140264834A1

公开(公告)日：2014-09-18

申请号：US13830570

申请日：2013-03-14

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hsin-Yu Chen ,  Lin-Chih Huang ,  Tasi-Jung Wu ,  Tsang-Jiuh Wu ,  Wen-Chih Chiou

IPC: H01L23/00

CPC classification number: H01L24/14 ,  H01L21/6835 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53238 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/96 ,  H01L25/0657 ,  H01L2221/68359 ,  H01L2221/68381 ,  H01L2224/11424 ,  H01L2224/11464 ,  H01L2224/13025 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/81005 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2224/96 ,  H01L2924/06 ,  H01L2924/07025 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/01047 ,  H01L2224/81

Abstract: Methods of making and an integrated circuit device. An embodiment method includes patterning a first polymer layer disposed over a first copper seed layer, electroplating a through polymer via in the first polymer layer using the first copper seed layer, a via end surface offset from a first polymer layer surface, forming a second polymer layer over the first polymer layer, the second polymer layer patterned to expose the via end surface, and electroplating an interconnect in the second polymer layer to cap the via end surface using a second copper seed layer.

Abstract translation: 制造方法和集成电路器件。 一种实施方式包括图案化设置在第一铜籽晶层上的第一聚合物层，使用第一铜籽晶层在第一聚合物层中电镀穿过聚合物通孔，从第一聚合物层表面偏移的通孔端表面，形成第二聚合物 在第一聚合物层上方形成第二聚合物层，第二聚合物层图案化以暴露通孔端面，以及在第二聚合物层中电镀互连以通过第二铜种子层覆盖通孔端面。