公开(公告)号：US11961820B2

公开(公告)日：2024-04-16

申请号：US16768208

申请日：2019-02-05

申请人： OSRAM OLED GmbH

发明人： Simeon Katz ,  Mathias Wendt ,  Sophia Huppmann ,  Marcus Zenger ,  Jens Mueller

IPC分类号： H01L23/00 ,  H01L33/62

CPC分类号： H01L24/89 ,  H01L24/05 ,  H01L24/08 ,  H01L33/62 ,  H01L2224/05166 ,  H01L2224/05169 ,  H01L2224/05582 ,  H01L2224/05611 ,  H01L2224/05644 ,  H01L2224/08111 ,  H01L2224/08146 ,  H01L2224/08502 ,  H01L2224/80805 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/12041 ,  H01L2933/0066

摘要： A method for producing a connection between component parts and a component made of component parts are disclosed. In an embodiment, a includes providing a first component part having a first exposed insulation layer and a second component part having a second exposed insulation layer, wherein each of the insulation layers has at least one opening, joining together the first and second component parts such that the opening of the first insulation layer and the opening of the second insulation layer overlap in top view, wherein an Au layer and a Sn layer are arranged one above the other in at least one of the openings and melting the Au layer and the Sn layer to form an AuSn alloy, wherein the AuSn alloy forms a through-via after cooling electrically conductively connecting the first component part to the second component part.

公开(公告)号：US20240120303A1

公开(公告)日：2024-04-11

申请号：US17980568

申请日：2022-11-04

申请人： United Microelectronics Corp.

发明人： Chien-Ming Lai

IPC分类号： H01L23/00 ,  H01L23/498

CPC分类号： H01L24/08 ,  H01L23/49822 ,  H01L2224/08111 ,  H01L2224/08147

摘要： A semiconductor structure including a first substrate, a first conductive layer, and first bonding pads is provided. The first conductive layer is located on the first substrate. The first conductive layer includes a main body portion and an extension portion. The extension portion is connected to the main body portion and includes a terminal portion away from the main body portion. The first bonding pads are connected to the main body portion and the extension portion. The number of the first bonding pads connected to the terminal portion of the extension portion is plural.

公开(公告)号：US20180151546A1

公开(公告)日：2018-05-31

申请号：US15409385

申请日：2017-01-18

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Jing-Cheng LIN ,  Po-Hao TSAI

IPC分类号： H01L25/11 ,  H01L25/065 ,  H01L23/498 ,  H01L23/31 ,  H01L23/00 ,  H01L21/768 ,  H01L21/56 ,  H01L21/02

CPC分类号： H01L25/117 ,  H01L21/02354 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/76883 ,  H01L22/14 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/562 ,  H01L24/03 ,  H01L24/09 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/81 ,  H01L24/83 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68359 ,  H01L2224/02331 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05573 ,  H01L2224/05647 ,  H01L2224/08111 ,  H01L2224/13021 ,  H01L2224/1308 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/32013 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49113 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/83005 ,  H01L2224/83102 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/0652 ,  H01L2225/06548 ,  H01L2225/06568 ,  H01L2225/06586 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/18161 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2224/81 ,  H01L2224/83

摘要： A package structure includes a semiconductor device, a first dielectric layer, a redistribution line and a conductive bump. The first dielectric layer is over the semiconductor device and has first and second openings on opposite surfaces of the first dielectric layer, wherein the first and second openings taper in substantially opposite direction. The redistribution line is partially in the first opening of the first dielectric layer and electrically connected to the semiconductor device. The conductive bump is partially embeddedly retained in the second opening and electrically connected to the redistribution line.

公开(公告)号：US20150325538A1

公开(公告)日：2015-11-12

申请号：US14699411

申请日：2015-04-29

申请人： TOYOTA JIDOSHA KABUSHIKI KAISHA

发明人： Kazuya ASAOKA ,  Norio FUJITSUKA ,  Takashi OZAKI ,  Kenichi AO

IPC分类号： H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L21/302

CPC分类号： H01L23/564 ,  B81C1/00238 ,  B81C1/00269 ,  B81C2203/0118 ,  B81C2203/019 ,  H01L21/302 ,  H01L23/3157 ,  H01L23/3171 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/30 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/89 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0311 ,  H01L2224/0331 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/05567 ,  H01L2224/05571 ,  H01L2224/08111 ,  H01L2224/08146 ,  H01L2224/10145 ,  H01L2224/10175 ,  H01L2224/13021 ,  H01L2224/131 ,  H01L2224/13138 ,  H01L2224/1601 ,  H01L2224/16145 ,  H01L2224/16147 ,  H01L2224/16148 ,  H01L2224/26145 ,  H01L2224/26175 ,  H01L2224/29011 ,  H01L2224/29013 ,  H01L2224/29021 ,  H01L2224/291 ,  H01L2224/29138 ,  H01L2224/30131 ,  H01L2224/30135 ,  H01L2224/30136 ,  H01L2224/30177 ,  H01L2224/3201 ,  H01L2224/32145 ,  H01L2224/32147 ,  H01L2224/32148 ,  H01L2224/73103 ,  H01L2224/73204 ,  H01L2224/80001 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81365 ,  H01L2224/81385 ,  H01L2224/81801 ,  H01L2224/81805 ,  H01L2224/83193 ,  H01L2224/83203 ,  H01L2224/83365 ,  H01L2224/83385 ,  H01L2224/83801 ,  H01L2224/83805 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06555 ,  H01L2924/163 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2224/81 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/013 ,  H01L2224/83 ,  H01L2924/00

摘要： The method for producing a semiconductor device includes: forming an opening in an area of at least one of the complementary metal-oxide semiconductor wafer that includes a first part and the other semiconductor wafer that includes a second part, the opening terminating within the area and not penetrating through the area, the area including corresponding one of the first part and the second part and an outer peripheral part of the corresponding one of the first part and the second part; forming a conduction hole within the first part, the conduction hole communicating with a metallic material in the complementary metal-oxide semiconductor wafer; arranging a first joining material inside the conduction hole and on the first part, and a second joining material on the second part; and joining the arranged first joining material and the arranged second joining material.

摘要翻译： 制造半导体器件的方法包括：在包括第一部分的互补金属氧化物半导体晶片中的至少一个区域和包括第二部分的另一个半导体晶片的区域中形成开口，该开口终止于该区域内， 所述区域不包括所述区域，所述区域包括所述第一部分和所述第二部分中的相应一个和所述第一部分和所述第二部分中的相应一个的外周部分; 在所述第一部分内形成导通孔，所述导电孔与所述互补金属氧化物半导体晶片中的金属材料连通; 在所述导通孔和所述第一部分内布置第一接合材料，以及在所述第二部分上布置第二接合材料; 并且将所述布置的第一接合材料和所述布置的第二接合材料接合。

公开(公告)号：US20160013099A1

公开(公告)日：2016-01-14

申请号：US14718435

申请日：2015-05-21

申请人： Kabushiki Kaisha Toshiba

发明人： Kazumasa TANIDA ,  Takamitsu YOSHIDA ,  Kuniaki UTSUMI ,  Atsuko KAWASAKI

IPC分类号： H01L21/768 ,  H01L25/065 ,  H01L21/283 ,  H01L23/498 ,  H01L21/48

CPC分类号： H01L21/4853 ,  H01L21/76885 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L27/14634 ,  H01L27/14643 ,  H01L2224/03462 ,  H01L2224/03616 ,  H01L2224/03831 ,  H01L2224/05547 ,  H01L2224/05557 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/08059 ,  H01L2224/08111 ,  H01L2224/08121 ,  H01L2224/08147 ,  H01L2224/80203 ,  H01L2224/80345 ,  H01L2224/80365 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/00 ,  H01L2924/00014

摘要： According to embodiments, a semiconductor device is provided. The semiconductor device includes an insulation layer, an electrode, and a groove. The insulation layer is provided on a surface of a substrate. The electrode is buried in the insulation layer, and a first end surface of the electrode is exposed from the insulation layer. The groove is formed around the electrode on the surface of the substrate. The groove has an outside surface of the electrode as one side surface, and the groove is opened on the surface side of the insulation layer. The first end surface of the electrode buried in the insulation layer protrudes from the surface of the insulation layer.

摘要翻译： 根据实施例，提供一种半导体器件。 半导体器件包括绝缘层，电极和沟槽。 绝缘层设置在基板的表面上。 电极被埋在绝缘层中，电极的第一端面从绝缘层露出。 在基板表面上的电极周围形成凹槽。 凹槽具有作为一个侧面的电极的外表面，并且在绝缘层的表面侧上开槽。 埋在绝缘层中的电极的第一端面从绝缘层的表面突出。

公开(公告)号：US20150187742A1

公开(公告)日：2015-07-02

申请号：US14404005

申请日：2013-05-09

申请人： NEPES CO., LTD.

发明人： Yong-Tae Kwon ,  Kyung-Hoon Park

IPC分类号： H01L25/10 ,  H01L23/00 ,  H01L25/065 ,  H01L21/56 ,  H01L23/31 ,  H01L23/498

CPC分类号： H01L25/105 ,  H01L21/56 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/08 ,  H01L24/19 ,  H01L24/24 ,  H01L24/32 ,  H01L24/82 ,  H01L24/83 ,  H01L24/89 ,  H01L25/0655 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/08111 ,  H01L2224/08235 ,  H01L2224/12105 ,  H01L2224/24101 ,  H01L2224/24155 ,  H01L2224/32235 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/12042 ,  H01L2924/171 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/00

摘要： Provided is a method of manufacturing a semiconductor package including a through wiring having precision and a low process defect. The semiconductor package includes an insulating substrate including a first through portion and a second through portion; a through wiring which fills the first through portion, and is located to penetrate the insulating substrate; a semiconductor chip which is located in the second through portion, and is electrically connected to the through wiring; a molding member molding the semiconductor chip and the insulating substrate; and a re-wiring pattern layer which is located at a lower side of the insulating substrate, and electrically connects the through wiring and the semiconductor chip.

摘要翻译： 提供一种制造半导体封装的方法，该半导体封装包括具有精度和低工艺缺陷的贯通布线。 半导体封装包括包括第一通孔部分和第二贯通部分的绝缘基板; 贯通配线，其填充所述第一贯通部，并且位于所述绝缘基板上; 半导体芯片，其位于所述第二贯通部分中，并且与所述贯通布线电连接; 模制所述半导体芯片和所述绝缘基板的模制构件; 以及重新布线图案层，其位于绝缘基板的下侧，并且电连接通孔布线和半导体芯片。

公开(公告)号：US09070691B2

公开(公告)日：2015-06-30

申请号：US14341288

申请日：2014-07-25

申请人： SK HYNIX INC.

发明人： Jae Sung Oh ,  Moon Un Hyun ,  Jong Hyun Kim ,  Jin Ho Gwon

IPC分类号： H01L23/02 ,  H01L23/48 ,  H01L23/52 ,  H01L23/04 ,  H01L29/40 ,  H01L23/538 ,  H01L21/48 ,  H01L21/673 ,  H01L23/32 ,  H01L25/10 ,  H01L25/11 ,  H01L23/31 ,  H01L23/498

CPC分类号： H01L23/5386 ,  H01L21/486 ,  H01L21/67346 ,  H01L23/3128 ,  H01L23/32 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/5384 ,  H01L25/105 ,  H01L25/117 ,  H01L2224/08111 ,  H01L2224/16225 ,  H01L2224/29009 ,  H01L2224/29011 ,  H01L2224/32146 ,  H01L2225/1023 ,  H01L2225/107 ,  H01L2924/01087

摘要： A semiconductor package includes a substrate having a substrate body possessing a first region, a second region which is defined around the first region and a third region which is defined around the second region. Wiring lines are placed on the substrate body, and the wiring lines have first ends that extend to the third region. Connection patterns are placed in the third region and are electrically connected to the first ends of the wiring lines. A to semiconductor chip is disposed in the first region and is electrically connected to the respective wiring lines, and a molding member is disposed in the first and second regions and covers the semiconductor chip.

摘要翻译： 半导体封装包括具有第一区域的基板主体的基板，围绕第一区域限定的第二区域和围绕第二区域限定的第三区域。 布线被放置在基板主体上，并且布线具有延伸到第三区域的第一端。 连接图案被放置在第三区域中并且电连接到布线的第一端。 A至半导体芯片设置在第一区域中并与各布线电连接，并且模制构件设置在第一和第二区域中并且覆盖半导体芯片。

公开(公告)号：US20140015088A1

公开(公告)日：2014-01-16

申请号：US13934683

申请日：2013-07-03

申请人： STMicroelectronics (Crolles 2) SAS

发明人： Laurent-Luc Chapelon

IPC分类号： H01L27/04

CPC分类号： H01L27/04 ,  G01K5/56 ,  H01L22/34 ,  H01L24/05 ,  H01L24/08 ,  H01L24/80 ,  H01L2224/05546 ,  H01L2224/05547 ,  H01L2224/05571 ,  H01L2224/0603 ,  H01L2224/06102 ,  H01L2224/08057 ,  H01L2224/08111 ,  H01L2224/08121 ,  H01L2224/08147 ,  H01L2224/80012 ,  H01L2224/80097 ,  H01L2224/80141 ,  H01L2224/80357 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/80986 ,  H01L2924/00014 ,  H01L2224/05552

摘要： A three-dimensional integrated structure is formed from a first integrated circuit with a first cavity filled with a first conductive material and a second integrated circuit with a second cavity filled with a second conductive material, the second cavity facing the first cavity. The filled first cavity forms a first element and the filled second cavity forms a second element, the first and second elements separated from each other by a cavity. The first and second conductive materials have different thermal expansion coefficients. A contact detection circuit is electrically connected to the filled first and second cavities, and is operable to sense electrical contact between the first and second conductive materials in response to a change in temperature.

摘要翻译： 三维集成结构由具有填充有第一导电材料的第一空腔的第一集成电路和具有填充有第二导电材料的第二空腔的第二集成电路形成，第二空腔面对第一空腔。 填充的第一空腔形成第一元件，并且填充的第二空腔形成第二元件，第一元件和第二元件通过空腔彼此分离。 第一和第二导电材料具有不同的热膨胀系数。 接触检测电路电连接到填充的第一和第二空腔，并且可操作以响应于温度变化来感测第一和第二导电材料之间的电接触。

公开(公告)号：US20100072598A1

公开(公告)日：2010-03-25

申请号：US12347005

申请日：2008-12-31

申请人： Jae Sung OH ,  Moon Un HYUN ,  Jong Hyun KIM ,  Jin Ho Gwon ,  Dong You KIM ,  Ki Bon CHA

发明人： Jae Sung OH ,  Moon Un HYUN ,  Jong Hyun KIM ,  Jin Ho Gwon ,  Dong You KIM ,  Ki Bon CHA

IPC分类号： H01L23/538 ,  H01L23/48

CPC分类号： H01L23/5386 ,  H01L21/486 ,  H01L21/67346 ,  H01L23/3128 ,  H01L23/32 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/5384 ,  H01L25/105 ,  H01L25/117 ,  H01L2224/08111 ,  H01L2224/16225 ,  H01L2224/29009 ,  H01L2224/29011 ,  H01L2224/32146 ,  H01L2225/1023 ,  H01L2225/107 ,  H01L2924/01087

摘要： A semiconductor package includes a substrate having a substrate body possessing a first region, a second region which is defined around the first region and a third region which is defined around the second region. Wiring lines are placed on the substrate body, and the wiring lines have first ends that extend to the third region. Connection patterns are placed in the third region and are electrically connected to the first ends of the wiring lines. A semiconductor chip is disposed in the first region and is electrically connected to the respective wiring lines, and a molding member is disposed in the first and second regions and covers the semiconductor chip.

摘要翻译： 半导体封装包括具有第一区域的基板主体的基板，围绕第一区域限定的第二区域和围绕第二区域限定的第三区域。 布线被放置在基板主体上，并且布线具有延伸到第三区域的第一端。 连接图案被放置在第三区域中并且电连接到布线的第一端。 半导体芯片设置在第一区域中并且电连接到各个布线，并且模制构件设置在第一和第二区域中并且覆盖半导体芯片。

公开(公告)号：US20240304530A1

公开(公告)日：2024-09-12

申请号：US18425703

申请日：2024-01-29

申请人： FUJI ELECTRIC CO., LTD.

发明人： Hisato INOKUCHI

IPC分类号： H01L23/495 ,  H01L23/00 ,  H01L23/373 ,  H01L25/065 ,  H02M7/00

CPC分类号： H01L23/49575 ,  H01L23/3735 ,  H01L23/4951 ,  H01L23/4952 ,  H01L24/08 ,  H01L24/48 ,  H01L25/0652 ,  H02M7/003 ,  H01L2224/08111 ,  H01L2224/08145 ,  H01L2224/48138 ,  H01L2224/48147 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/13055 ,  H01L2924/13091

摘要： A power converter apparatus includes a first wire connected to first and second conductive portions on a substrate. The first wire includes first and second bonding portions that are bonded respectively to the first and second conductive portions and each have at opposite ends thereof respectively a bonding end and a joining end; and a wiring portion having opposite ends, to which the joining ends of the first and second bonding portions are connected and being located away from the front surface of the substrate. In a plan view, a first extending direction in which the first bonding portion extends is inclined at a first acute angle, from a first direction of a first line passing through the bonding ends of first and second bonding portions, toward a second direction of a force that acts on the first bonding portion due to thermal expansion of the sealing member.