公开(公告)号：US09793251B2

公开(公告)日：2017-10-17

申请号：US14955010

申请日：2015-11-30

申请人： NEPES CO., LTD.

发明人： Jun-Kyu Lee ,  Yong-Tae Kwon

IPC分类号： H01L21/52 ,  H01L23/31 ,  H01L23/498 ,  H01L25/16 ,  H01L23/00 ,  H01L23/13 ,  H01L21/56

CPC分类号： H01L25/16 ,  H01L21/568 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/24195 ,  H01L2924/13091 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1438 ,  H01L2924/1441 ,  H01L2924/15313 ,  H01L2924/182 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/37001

摘要： Disclosed herein is a semiconductor package in which a semiconductor chip and a mounting device are packaged together. The semiconductor package includes a semiconductor chip, a mounting block on which a first mounting device is mounted on a substrate that includes a circuit formed thereon, and an interconnection part configured to electrically connect the semiconductor chip to the mounting block.

公开(公告)号：US09502391B2

公开(公告)日：2016-11-22

申请号：US14404005

申请日：2013-05-09

申请人： NEPES CO., LTD.

发明人： Yong-Tae Kwon ,  Kyung-Hoon Park

IPC分类号： H01L23/02 ,  H01L25/10 ,  H01L23/00 ,  H01L23/538 ,  H01L21/56 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065

CPC分类号： H01L25/105 ,  H01L21/56 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/08 ,  H01L24/19 ,  H01L24/24 ,  H01L24/32 ,  H01L24/82 ,  H01L24/83 ,  H01L24/89 ,  H01L25/0655 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/08111 ,  H01L2224/08235 ,  H01L2224/12105 ,  H01L2224/24101 ,  H01L2224/24155 ,  H01L2224/32235 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/12042 ,  H01L2924/171 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/00

摘要： Provided is a method of manufacturing a semiconductor package including a through wiring having precision and a low process defect. The semiconductor package includes an insulating substrate including a first through portion and a second through portion; a through wiring which fills the first through portion, and is located to penetrate the insulating substrate; a semiconductor chip which is located in the second through portion, and is electrically connected to the through wiring; a molding member molding the semiconductor chip and the insulating substrate; and a re-wiring pattern layer which is located at a lower side of the insulating substrate, and electrically connects the through wiring and the semiconductor chip.

摘要翻译： 提供一种制造半导体封装的方法，该半导体封装包括具有精度和低工艺缺陷的贯通布线。 半导体封装包括包括第一通孔部分和第二贯通部分的绝缘基板; 贯通配线，其填充所述第一贯通部，并且位于所述绝缘基板上; 半导体芯片，其位于所述第二贯通部分中，并且与所述贯通布线电连接; 模制所述半导体芯片和所述绝缘基板的模制构件; 以及重新布线图案层，其位于绝缘基板的下侧，并且电连接通孔布线和半导体芯片。

公开(公告)号：US20160190108A1

公开(公告)日：2016-06-30

申请号：US14955010

申请日：2015-11-30

申请人： NEPES CO., LTD.

发明人： Jun-Kyu Lee ,  Yong-Tae Kwon

IPC分类号： H01L25/16 ,  H01L23/31 ,  H01L23/00 ,  H01L25/065 ,  H01L21/52 ,  H01L21/56 ,  H01L21/768 ,  H01L23/498 ,  H01L25/00

CPC分类号： H01L25/16 ,  H01L21/568 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/24195 ,  H01L2924/13091 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1438 ,  H01L2924/1441 ,  H01L2924/15313 ,  H01L2924/182 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/37001

摘要： Disclosed herein is a semiconductor package in which a semiconductor chip and a mounting device are packaged together. The semiconductor package includes a semiconductor chip, a mounting block on which a first mounting device is mounted on a substrate that includes a circuit formed thereon, and an interconnection part configured to electrically connect the semiconductor chip to the mounting block.

摘要翻译： 这里公开了将半导体芯片和安装装置封装在一起的半导体封装。 半导体封装包括半导体芯片，安装块，第一安装装置安装在其上形成有电路的基板上，以及配置为将半导体芯片电连接到安装块的互连部件。

公开(公告)号：US11450535B2

公开(公告)日：2022-09-20

申请号：US16090602

申请日：2017-04-03

申请人： NEPES CO., LTD.

发明人： Yong-Tae Kwon ,  Jun-Kyu Lee ,  Si Woo Lim ,  Dong-Hoon Oh ,  Jun-Sung Ma ,  Tae-Won Kim

IPC分类号： H01L21/56 ,  H01L21/683 ,  H01L23/31 ,  H01L23/498 ,  H01L23/552 ,  H01L23/522 ,  H01L23/525

摘要： A semiconductor package comprising a fan-out structure and a manufacturing method therefor are disclosed. A semiconductor package according to an embodiment of the present invention comprises: a wiring unit comprising an insulation layer and a wiring layer; a semiconductor chip mounted on the wiring unit and coupled to the wiring layer by flip-chip bonding; a filling member for filling a gap between the semiconductor chip and the wiring unit; and a film member for performing coating so as to cover one surface of each of the semiconductor chip, the filling member, and the wiring unit.

公开(公告)号：US20150137346A1

公开(公告)日：2015-05-21

申请号：US14369807

申请日：2012-12-28

申请人： NEPES CO., LTD.

发明人： Yong-Tae Kwon ,  Jun-Kyu Lee

IPC分类号： H01L23/538 ,  H01L23/00 ,  H01L21/56

CPC分类号： H01L23/5389 ,  H01L21/565 ,  H01L23/3128 ,  H01L24/19 ,  H01L24/24 ,  H01L24/82 ,  H01L25/0657 ,  H01L2224/02372 ,  H01L2224/02375 ,  H01L2224/02379 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/06182 ,  H01L2224/1134 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/24 ,  H01L2224/82 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06565 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/00 ,  H01L2924/00014

摘要： Disclosed herein is a stacked semiconductor package in which semiconductor chips having various sizes are stacked. In accordance with one aspect of the present disclosure, a stacked semiconductor package includes a first semiconductor chip structure provided with a first semiconductor chip, a first mold layer surrounding the first semiconductor chip, and a first penetration electrode passing through the first mold layer and electrically connected to the first semiconductor chip, and a second semiconductor chip structure vertically stacked on the first semiconductor chip structure and provided with a second semiconductor chip and a second penetration electrode electrically connected to the first penetration electrode, wherein the first semiconductor chip structure may have the same size as the second semiconductor chip structure.

摘要翻译： 这里公开了堆叠半导体封装，其中堆叠了各种尺寸的半导体芯片。 根据本公开的一个方面，堆叠半导体封装包括：第一半导体芯片结构，设置有第一半导体芯片，围绕第一半导体芯片的第一模制层和穿过第一模具层的第一穿透电极， 连接到第一半导体芯片，以及垂直堆叠在第一半导体芯片结构上的第二半导体芯片结构，并且设置有电连接到第一穿透电极的第二半导体芯片和第二贯穿电极，其中第一半导体芯片结构可以具有 与第二半导体芯片结构相同的尺寸。

公开(公告)号：US09754892B2

公开(公告)日：2017-09-05

申请号：US14369807

申请日：2012-12-28

申请人： NEPES CO., LTD.

发明人： Yong-Tae Kwon ,  Jun-Kyu Lee

IPC分类号： H01L23/34 ,  H01L23/538 ,  H01L25/065 ,  H01L23/00 ,  H01L21/56 ,  H01L23/31

CPC分类号： H01L23/5389 ,  H01L21/565 ,  H01L23/3128 ,  H01L24/19 ,  H01L24/24 ,  H01L24/82 ,  H01L25/0657 ,  H01L2224/02372 ,  H01L2224/02375 ,  H01L2224/02379 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/06182 ,  H01L2224/1134 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/24 ,  H01L2224/82 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06565 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/00 ,  H01L2924/00014

摘要： Disclosed herein is a stacked semiconductor package in which semiconductor chips having various sizes are stacked. In accordance with one aspect of the present disclosure, a stacked semiconductor package includes a first semiconductor chip structure provided with a first semiconductor chip, a first mold layer surrounding the first semiconductor chip, and a first penetration electrode passing through the first mold layer and electrically connected to the first semiconductor chip, and a second semiconductor chip structure vertically stacked on the first semiconductor chip structure and provided with a second semiconductor chip and a second penetration electrode electrically connected to the first penetration electrode, wherein the first semiconductor chip structure may have the same size as the second semiconductor chip structure.

公开(公告)号：US09653397B2

公开(公告)日：2017-05-16

申请号：US14866725

申请日：2015-09-25

申请人： NEPES CO., LTD.

发明人： Yong-Tae Kwon ,  Jun-Kyu Lee

IPC分类号： H01L23/528 ,  H01L21/768 ,  H01L23/522 ,  H01L23/538 ,  H01L21/48 ,  H01L23/00 ,  H01L25/10 ,  H01L25/00 ,  H01L23/498 ,  H01L21/56 ,  H01L23/48

CPC分类号： H01L23/528 ,  H01L21/486 ,  H01L21/568 ,  H01L21/76829 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/522 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/19 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/24227 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/15311

摘要： Disclosed herein are a semiconductor package and a method of manufacturing the same, which allows a conductive path to be provided to connect upper and lower portions of the semiconductor package. A semiconductor package according to the present invention includes a semiconductor chip, a substrate including an accommodating portion to accommodate the semiconductor chip, a sealing material configured to mold the semiconductor chip and the substrate to be integrated, a through wiring configured to vertically pass through the substrate, a wiring portion configured to electrically connect the semiconductor chip and one side of the through wiring, and an external connection portion to electrically connected to the other side of the through wiring and configured to be able to be electrically connected to an outside, wherein a wiring layer of the wiring portion is provided to be connected to the through wiring.

公开(公告)号：US20150187742A1

公开(公告)日：2015-07-02

申请号：US14404005

申请日：2013-05-09

申请人： NEPES CO., LTD.

发明人： Yong-Tae Kwon ,  Kyung-Hoon Park

IPC分类号： H01L25/10 ,  H01L23/00 ,  H01L25/065 ,  H01L21/56 ,  H01L23/31 ,  H01L23/498

CPC分类号： H01L25/105 ,  H01L21/56 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/08 ,  H01L24/19 ,  H01L24/24 ,  H01L24/32 ,  H01L24/82 ,  H01L24/83 ,  H01L24/89 ,  H01L25/0655 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/08111 ,  H01L2224/08235 ,  H01L2224/12105 ,  H01L2224/24101 ,  H01L2224/24155 ,  H01L2224/32235 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/12042 ,  H01L2924/171 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/00

摘要： Provided is a method of manufacturing a semiconductor package including a through wiring having precision and a low process defect. The semiconductor package includes an insulating substrate including a first through portion and a second through portion; a through wiring which fills the first through portion, and is located to penetrate the insulating substrate; a semiconductor chip which is located in the second through portion, and is electrically connected to the through wiring; a molding member molding the semiconductor chip and the insulating substrate; and a re-wiring pattern layer which is located at a lower side of the insulating substrate, and electrically connects the through wiring and the semiconductor chip.

摘要翻译： 提供一种制造半导体封装的方法，该半导体封装包括具有精度和低工艺缺陷的贯通布线。 半导体封装包括包括第一通孔部分和第二贯通部分的绝缘基板; 贯通配线，其填充所述第一贯通部，并且位于所述绝缘基板上; 半导体芯片，其位于所述第二贯通部分中，并且与所述贯通布线电连接; 模制所述半导体芯片和所述绝缘基板的模制构件; 以及重新布线图案层，其位于绝缘基板的下侧，并且电连接通孔布线和半导体芯片。