公开(公告)号：US12127393B2

公开(公告)日：2024-10-22

申请号：US17539742

申请日：2021-12-01

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Tao Yang ,  Dongxue Zhao ,  Yuancheng Yang ,  Zhiliang Xia ,  Zongliang Huo

IPC: H01L29/66 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18 ,  H01L29/78 ,  H10B12/00

CPC classification number: H10B12/33 ,  H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L29/66666 ,  H01L29/7827 ,  H10B12/036 ,  H10B12/05 ,  H10B12/482 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/1441 ,  H01L2924/1444

Abstract: In certain aspects, a memory device includes a vertical transistor, a storage unit, a bit line, and a body line. The vertical transistor includes a semiconductor body extending in a first direction. The semiconductor body includes a doped source, a doped drain, and a channel portion. The storage unit is coupled to a first terminal. The first terminal is one of the source and the drain. The bit line extends in a second direction perpendicular to the first direction and coupled to a second terminal. The second terminal is another one of the source and the drain. The body line is coupled to the channel portion of the semiconductor body.

公开(公告)号：US20240274184A1

公开(公告)日：2024-08-15

申请号：US18632024

申请日：2024-04-10

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege ,  Mingdong Cui

IPC: G11C11/408 ,  G11C11/22 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: G11C11/4085 ,  G11C11/221 ,  G11C11/2257 ,  G11C11/2259 ,  G11C11/4087 ,  H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/1441

Abstract: Methods, systems, and devices for word line drivers for multiple-die memory devices are described. A memory device may include a first semiconductor die associated with at least memory cells and corresponding access lines of the memory device, and a second semiconductor die associated with at least access line driver circuitry of the memory device. The second semiconductor die may be located in contact with or otherwise adjacent to the first semiconductor die, and electrical contacts may be formed to couple the access line driver circuitry of the second semiconductor die with the access line conductors of the first semiconductor die. For example, cavities may be formed through the second semiconductor die and at least a portion of the first semiconductor die, and the electrical contacts may be formed between the semiconductor dies at least in part from forming a conductive material in the cavities.

公开(公告)号：US12051663B2

公开(公告)日：2024-07-30

申请号：US17344946

申请日：2021-06-11

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Meng-Han Lin ,  Sai-Hooi Yeong ,  Yu-Ming Lin

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/00 ,  H01L25/18

CPC classification number: H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/1431 ,  H01L2924/1441

Abstract: A memory device includes a staircase structure, a plurality of first conductive contacts, a plurality of first drivers and a plurality of second conductive contacts. The staircase structure includes a plurality of first conductive lines and a plurality of first dielectric layers stacked alternately. The first conductive contacts are electrically connected to the plurality of first conductive lines respectively. The second conductive contacts are electrically connected to the plurality of first drivers respectively. The plurality of first conductive contacts and the plurality of second conductive contacts are bonded and disposed between the plurality of first conductive lines and the plurality of first drivers.

公开(公告)号：US12026034B1

公开(公告)日：2024-07-02

申请号：US17472330

申请日：2021-09-10

Applicant: Kepler Computing Inc.

Inventor： Amrita Mathuriya ,  Christopher B. Wilkerson ,  Rajeev Kumar Dokania ,  Debo Olaosebikan ,  Sasikanth Manipatruni

IPC: G06F1/32 ,  G06F1/329 ,  H01L23/48 ,  H01L23/498 ,  H01L23/538 ,  G06N20/00

CPC classification number: G06F1/329 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/5385 ,  H01L23/5386 ,  G06N20/00 ,  H01L2924/14335 ,  H01L2924/1438 ,  H01L2924/1441

Abstract: A packaging technology to improve performance of an AI processing system resulting in an ultra-high bandwidth system. An IC package is provided which comprises: a substrate; a first die on the substrate, and a second die stacked over the first die. The first die can be a first logic die (e.g., a compute chip, CPU, GPU, etc.) while the second die can be a compute chiplet comprising ferroelectric or paraelectric logic. Both dies can include ferroelectric or paraelectric logic. The ferroelectric/paraelectric logic may include AND gates, OR gates, complex gates, majority, minority, and/or threshold gates, sequential logic, etc. The IC package can be in a 3D or 2.5D configuration that implements logic-on-logic stacking configuration. The 3D or 2.5D packaging configurations have chips or chiplets designed to have time distributed or spatially distributed processing. The logic of chips or chiplets is segregated so that one chip in a 3D or 2.5D stacking arrangement is hot at a time.

公开(公告)号：US20240186231A1

公开(公告)日：2024-06-06

申请号：US18520453

申请日：2023-11-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jihwang KIM ,  Joonsung KIM ,  Sangjin Baek ,  Kyounglim Suk

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L23/522 ,  H01L25/065

CPC classification number: H01L23/49822 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/5226 ,  H01L24/08 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/08235 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/06544 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1438 ,  H01L2924/1441 ,  H01L2924/181

Abstract: A semiconductor package includes a lower redistribution structure. A semiconductor device is disposed on the lower redistribution structure. A lower encapsulant is disposed on the lower redistribution structure and surrounds a side surface of the semiconductor device. An upper composite redistribution structure is disposed on an upper portion of the semiconductor device and includes a primary conductive structure, a secondary conductive structure disposed on the primary conductive structure, connection vias disposed between the primary conductive structure and the secondary conductive structure, and an upper encapsulant disposed between the primary conductive structure and the secondary conductive structure and surrounding the connection vias.

公开(公告)号：US20240162181A1

公开(公告)日：2024-05-16

申请号：US18486831

申请日：2023-10-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sun Jae KIM ,  Sun Kyoung SEO ,  Cha Jea JO

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/544 ,  H01L25/065 ,  H01L25/18 ,  H10B80/00

CPC classification number: H01L24/17 ,  H01L23/49838 ,  H01L23/544 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/18 ,  H10B80/00 ,  H01L24/03 ,  H01L24/11 ,  H01L24/33 ,  H01L2223/54426 ,  H01L2224/0346 ,  H01L2224/03466 ,  H01L2224/05011 ,  H01L2224/05015 ,  H01L2224/05018 ,  H01L2224/05024 ,  H01L2224/05073 ,  H01L2224/05166 ,  H01L2224/05541 ,  H01L2224/05551 ,  H01L2224/05552 ,  H01L2224/05553 ,  H01L2224/05555 ,  H01L2224/0557 ,  H01L2224/05573 ,  H01L2224/05655 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/06181 ,  H01L2224/1146 ,  H01L2224/11849 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13118 ,  H01L2224/1312 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/1403 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/17517 ,  H01L2224/2929 ,  H01L2224/29386 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/04642 ,  H01L2924/0503 ,  H01L2924/0532 ,  H01L2924/0543 ,  H01L2924/05432 ,  H01L2924/05442 ,  H01L2924/0549 ,  H01L2924/059 ,  H01L2924/0665 ,  H01L2924/1431 ,  H01L2924/14361 ,  H01L2924/1437 ,  H01L2924/1441 ,  H01L2924/1443

Abstract: A semiconductor package comprising: a first semiconductor chip extending in each of first and second directions that intersect each other; a second semiconductor chip on the first semiconductor chip in a third direction perpendicular to the first and second directions, wherein the second semiconductor chip includes a first area and a second area that is adjacent to and extends around the first area; and a bump structure and a conductive material layer between the first and second semiconductor chips, wherein the conductive material layer is on the bump structure, wherein the bump structure includes a first bump structure overlapping the first area in the third direction, and a second bump structure overlapping the second area in the third direction, wherein the first and second bump structures are spaced apart from each other, and a thickness of the second bump structure is larger than a thickness of the first bump structure.

公开(公告)号：US11984150B2

公开(公告)日：2024-05-14

申请号：US17821646

申请日：2022-08-23

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege ,  Mingdong Cui

IPC: G11C11/40 ,  G11C11/22 ,  G11C11/408 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: G11C11/4085 ,  G11C11/221 ,  G11C11/2257 ,  G11C11/2259 ,  G11C11/4087 ,  H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/1441

Abstract: Methods, systems, and devices for word line drivers for multiple-die memory devices are described. A memory device may include a first semiconductor die associated with at least memory cells and corresponding access lines of the memory device, and a second semiconductor die associated with at least access line driver circuitry of the memory device. The second semiconductor die may be located in contact with or otherwise adjacent to the first semiconductor die, and electrical contacts may be formed to couple the access line driver circuitry of the second semiconductor die with the access line conductors of the first semiconductor die. For example, cavities may be formed through the second semiconductor die and at least a portion of the first semiconductor die, and the electrical contacts may be formed between the semiconductor dies at least in part from forming a conductive material in the cavities.

公开(公告)号：US20240079362A1

公开(公告)日：2024-03-07

申请号：US18104789

申请日：2023-02-02

Applicant: SK hynix Inc.

Inventor： Jin Won PARK

IPC: H01L23/00 ,  H01L23/528

CPC classification number: H01L24/09 ,  H01L23/528 ,  H01L24/08 ,  H01L2224/08055 ,  H01L2224/08056 ,  H01L2224/08112 ,  H01L2224/08121 ,  H01L2224/08147 ,  H01L2224/0903 ,  H01L2224/09051 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1441 ,  H01L2924/14511

Abstract: A semiconductor device may include: a first semiconductor structure including a first conductive layer and four first bonding pads connected to the first conductive layer; and a second semiconductor structure including a second conductive layer and four second bonding pads connected to the second conductive layer, wherein the four first bonding pads are configured to be disposed to have respective centers each overlapping four intersections that are formed by two virtual first straight lines extending in parallel in a first direction and two virtual second straight lines extending in parallel in a second direction intersecting the first direction, where each of the four first bonding pads has four quadrants divided by the first straight line and the second straight line, and wherein, when the first semiconductor structure and the second semiconductor structure are normally aligned, the four second bonding pads are configured to be disposed to have respective centers that are displaced in directions from the respective centers of the four first bonding pads toward different quadrants.

公开(公告)号：US20240071466A1

公开(公告)日：2024-02-29

申请号：US17821646

申请日：2022-08-23

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege ,  Mingdong Cui

IPC: G11C11/408 ,  G11C11/22 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: G11C11/4085 ,  G11C11/221 ,  G11C11/2257 ,  G11C11/2259 ,  G11C11/4087 ,  H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/1441

Abstract: Methods, systems, and devices for word line drivers for multiple-die memory devices are described. A memory device may include a first semiconductor die associated with at least memory cells and corresponding access lines of the memory device, and a second semiconductor die associated with at least access line driver circuitry of the memory device. The second semiconductor die may be located in contact with or otherwise adjacent to the first semiconductor die, and electrical contacts may be formed to couple the access line driver circuitry of the second semiconductor die with the access line conductors of the first semiconductor die. For example, cavities may be formed through the second semiconductor die and at least a portion of the first semiconductor die, and the electrical contacts may be formed between the semiconductor dies at least in part from forming a conductive material in the cavities.

公开(公告)号：US20230197553A1

公开(公告)日：2023-06-22

申请号：US18069957

申请日：2022-12-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： KYUNGDON MUN ,  DONGHWA KWAK ,  INHO ROH

IPC: H01L23/367 ,  H01L25/065 ,  H01L23/31 ,  H01L23/528 ,  H01L23/00

CPC classification number: H01L23/367 ,  H01L25/0657 ,  H01L23/3128 ,  H01L23/528 ,  H01L24/09 ,  H01L24/08 ,  H01L24/17 ,  H01L24/16 ,  H01L24/33 ,  H01L24/32 ,  H01L2224/08112 ,  H01L2224/08113 ,  H01L2224/09181 ,  H01L2224/16148 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/32059 ,  H01L2224/32113 ,  H01L2224/32145 ,  H01L2224/32227 ,  H01L2224/33051 ,  H01L2924/10161 ,  H01L2924/1431 ,  H01L2924/14335 ,  H01L2924/141 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1441 ,  H01L2924/182

Abstract: A semiconductor package includes a package substrate, a first semiconductor chip mounted on the package substrate and that includes a first semiconductor substrate that includes through electrodes, and a second semiconductor chip disposed on the first semiconductor chip and that includes a second semiconductor substrate that includes an active surface and an inactive surface. The second semiconductor chip further includes a plurality of isolated heat dissipation fins that extend in a vertical direction from the inactive surface.