公开(公告)号：US20240355768A1

公开(公告)日：2024-10-24

申请号：US18761443

申请日：2024-07-02

申请人： Intel Corporation

发明人： Adel A. Elsherbini ,  Krishna Bharath ,  Kevin P. O'Brien ,  Kimin Jun ,  Han Wui Then ,  Mohammad Enamul Kabir ,  Gerald S. Pasdast ,  Feras Eid ,  Aleksandar Aleksov ,  Johanna M. Swan ,  Shawna M. Liff

IPC分类号： H01L23/00 ,  H01L25/065

CPC分类号： H01L24/08 ,  H01L24/05 ,  H01L24/29 ,  H01L24/32 ,  H01L25/0657 ,  H01L28/10 ,  H01L2224/05147 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/0801 ,  H01L2224/08145 ,  H01L2224/0903 ,  H01L2224/09055 ,  H01L2224/09505 ,  H01L2224/29186 ,  H01L2224/32145

摘要： Disclosed herein are microelectronic assemblies including microelectronic components that are coupled together by direct bonding, as well as related structures and techniques. For example, in some embodiments, a microelectronic assembly may include a first microelectronic component and a second microelectronic component coupled to the first microelectronic component by a direct bonding region, wherein the direct bonding region includes at least part of an inductor.

公开(公告)号：US20240194560A1

公开(公告)日：2024-06-13

申请号：US18356838

申请日：2023-07-21

申请人： Western Digital Technologies, Inc.

发明人： Chee Seng Wong ,  Yoong Tatt Chin ,  Wei Chiat Teng

IPC分类号： H01L23/367 ,  H01L23/00 ,  H01L23/498 ,  H01L25/065 ,  H01L25/18 ,  H10B80/00

CPC分类号： H01L23/3672 ,  H01L23/49816 ,  H01L24/08 ,  H01L24/09 ,  H01L24/16 ,  H01L24/17 ,  H01L24/73 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/18 ,  H10B80/00 ,  H01L2224/08112 ,  H01L2224/08113 ,  H01L2224/0903 ,  H01L2224/16112 ,  H01L2224/16113 ,  H01L2224/16258 ,  H01L2224/1703 ,  H01L2224/17106 ,  H01L2224/80895 ,  H01L2224/81895 ,  H01L2924/1438 ,  H01L2924/1441 ,  H01L2924/15311

摘要： Technology for a memory device having memory dies flip-chip bonded to one or more interposers that are mounted to a system board is disclosed. The memory device may be an SSD and the system board may be an M.2 board. A memory controller die may be bonded to one of the interposer boards. In one aspect, the memory controller die is flip-chip bonded to the interposer board. In one aspect, a heat sink is attached to a top surface of the flip-chip bonded controller die and to top surfaces of a group of the memory dies. Neither the memory dies nor the interposers are covered with a mold compound. Performance of the memory device is improved by, for example, lower inductance and improved heat dissipation.

公开(公告)号：US20240128216A1

公开(公告)日：2024-04-18

申请号：US18149789

申请日：2023-01-04

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hao-Lin Yang ,  Kuan-Chieh Huang ,  Wei-Cheng Hsu ,  Tzu-Jui Wang ,  Ching-Chun Wang ,  Hsiao-Hui Tseng ,  Chen-Jong Wang ,  Dun-Nian Yaung

IPC分类号： H01L23/00 ,  H01L23/522 ,  H01L25/065

CPC分类号： H01L24/08 ,  H01L23/5226 ,  H01L24/03 ,  H01L24/09 ,  H01L25/0657 ,  H01L2224/03848 ,  H01L2224/08054 ,  H01L2224/08056 ,  H01L2224/08112 ,  H01L2224/08147 ,  H01L2224/0903 ,  H01L2924/12043 ,  H01L2924/1431 ,  H01L2924/1434

摘要： A bonding structure that may be used to form 3D-IC devices is formed using first oblong bonding pads on a first substrate and second oblong bonding pads one a second substrate. The first and second oblong bonding pads are laid crosswise, and the bond is formed. Viewed in a first cross-section, the first bonding pad is wider than the second bonding pad. Viewed in a second cross-section at a right angle to the first, the second bonding pad is wider than the first bonding pad. Making the bonding pads oblong and angling them relative to one another reduces variations in bonding area due to shifts in alignment between the first substrate and the second substrate. The oblong shape in a suitable orientation may also be used to reduce capacitive coupling between one of the bonding pads and nearby wires.

公开(公告)号：US20240071995A1

公开(公告)日：2024-02-29

申请号：US18212461

申请日：2023-06-21

申请人： Samsung Electronics Co., Ltd.

发明人： Raeyoung Kang ,  Minki Kim ,  Hyuekjae Lee

IPC分类号： H01L25/065 ,  H01L23/00 ,  H01L23/498 ,  H01L23/522 ,  H01L23/538

CPC分类号： H01L25/0652 ,  H01L23/49827 ,  H01L23/5226 ,  H01L23/5384 ,  H01L24/05 ,  H01L24/08 ,  H01L24/09 ,  H01L24/16 ,  H01L24/20 ,  H01L24/24 ,  H01L24/73 ,  H01L2224/05147 ,  H01L2224/08113 ,  H01L2224/08148 ,  H01L2224/0903 ,  H01L2224/09051 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/215 ,  H01L2224/24147 ,  H01L2224/24227 ,  H01L2224/73209 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1441

摘要： A semiconductor package includes a first semiconductor chip including a first semiconductor layer, a first through-electrode passing through the first semiconductor layer in a vertical direction, and a first bonding pad connected to the first through-electrode, and a second semiconductor chip including a second semiconductor layer on the first semiconductor chip, a wiring structure between the second semiconductor layer and the first semiconductor chip, a wiring pad connected to the wiring structure below the wiring structure, and a second bonding pad connected to the wiring pad below the wiring pad and in contact with the first bonding pad, wherein the second bonding pad includes a protrusion protruding toward the wiring pad.

公开(公告)号：US20240014116A1

公开(公告)日：2024-01-11

申请号：US17955557

申请日：2022-09-29

申请人： InnoLux Corporation

发明人： Chia-Lin YANG ,  Sheng-Nan CHEN ,  Kuang-Ming FAN ,  Kuan-Feng LEE ,  Jui-Jen YUEH ,  Chin-Ming HUANG

IPC分类号： H01L23/498 ,  H01L23/00 ,  H01L23/538 ,  H01L23/367

CPC分类号： H01L23/49838 ,  H01L24/08 ,  H01L24/09 ,  H01L23/49816 ,  H01L23/5386 ,  H01L23/3677 ,  H01L2224/0801 ,  H01L2224/08225 ,  H01L2224/0903 ,  H01L2924/30101

摘要： An electronic device includes an electronic unit, a circuit layer and a bonding pad. The electronic unit includes a chip, an insulating layer and a first conductor layer. The insulating layer is disposed on the chip, the insulating layer includes a first opening, and the first conductor layer is disposed in the first opening. The circuit layer is disposed corresponding to the electronic unit, and the circuit layer includes a second opening and a second conductor layer disposed in the second opening. The bonding pad is in contact with the second conductor layer, and the bonding pad is electrically connected to electronic unit. The first conductor layer has a first height, the second conductor layer has a second height, and a ratio of the first height to the second height is greater than or equal to 0.1 and less than or equal to 0.9.

公开(公告)号：US20230411327A1

公开(公告)日：2023-12-21

申请号：US18176474

申请日：2023-02-28

申请人： Kioxia Corporation

发明人： Masayoshi TAGAMI

IPC分类号： H01L23/00 ,  H10B80/00 ,  H01L25/16

CPC分类号： H01L24/08 ,  H10B80/00 ,  H01L24/09 ,  H01L24/05 ,  H01L25/16 ,  H01L2224/05005 ,  H01L2224/05014 ,  H01L2224/05018 ,  H01L2224/05073 ,  H01L2224/05573 ,  H01L2224/05541 ,  H01L2224/05558 ,  H01L2224/0903 ,  H01L2224/09051 ,  H01L2224/0801 ,  H01L2224/08055 ,  H01L2224/08057 ,  H01L2224/08145 ,  H01L2924/1438 ,  H01L2924/1431 ,  H01L2224/05647 ,  H01L2224/05554

摘要： According to one embodiment, a semiconductor device includes a first chip with a first electrode and a second electrode and a second chip with a third electrode and a fourth electrode. The first and second chips are bonded to each other with the first electrode contacting the third electrode and the second electrode contacting the fourth electrode. A thickness of the first electrode in a first direction perpendicular to a bonding interface between the first chip and the second chip is less than a thickness of the second electrode in the first direction. A planar area of the first electrode at the bonding interface is greater than a planar area of the second electrode at the bonding interface.

公开(公告)号：US20180122758A1

公开(公告)日：2018-05-03

申请号：US15503710

申请日：2016-05-06

申请人： BOE TECHNOLOGY GROUP CO., LTD.

发明人： Liqiang Chen ,  Huiji Zhou

IPC分类号： H01L23/00 ,  H01L27/12 ,  H01L25/18 ,  H01L25/00 ,  H01L23/544

CPC分类号： H01L24/09 ,  G02F1/13452 ,  G09G3/20 ,  H01L23/544 ,  H01L24/06 ,  H01L24/08 ,  H01L25/18 ,  H01L25/50 ,  H01L27/1218 ,  H01L27/124 ,  H01L2223/54426 ,  H01L2224/06132 ,  H01L2224/08052 ,  H01L2224/08145 ,  H01L2224/08225 ,  H01L2224/0903 ,  H01L2224/09132 ,  H01L2224/8013

摘要： Embodiments of the present application provide a display apparatus and a method for binding the same. The apparatus includes: a flexible display panel; and a chip on film bound on a binding region of the flexible display panel. The chip on film has at least two rows of output pads and the flexible display panel has at least two rows of input pads. Virtual elongation lines of all of the output pads intersect at a same intersection point in a first datum line perpendicular to the first direction. The output pads are electrically connected to the input pads and the output pads and the input pads have the virtual elongation lines at a same angle with respect to a common datum line, the common datum line being composed of the first datum line and the second datum line coinciding with each other.

公开(公告)号：US09960132B1

公开(公告)日：2018-05-01

申请号：US15503710

申请日：2016-05-06

申请人： BOE TECHNOLOGY GROUP CO., LTD.

发明人： Liqiang Chen ,  Huiji Zhou

IPC分类号： H01L51/52 ,  H01L23/00 ,  H01L25/18 ,  H01L27/12 ,  H01L25/00 ,  H01L23/544

CPC分类号： H01L24/09 ,  G02F1/13452 ,  G09G3/20 ,  H01L23/544 ,  H01L24/06 ,  H01L24/08 ,  H01L25/18 ,  H01L25/50 ,  H01L27/1218 ,  H01L27/124 ,  H01L2223/54426 ,  H01L2224/06132 ,  H01L2224/08052 ,  H01L2224/08145 ,  H01L2224/08225 ,  H01L2224/0903 ,  H01L2224/09132 ,  H01L2224/8013

摘要： Embodiments of the present application provide a display apparatus and a method for binding the same. The apparatus includes: a flexible display panel; and a chip on film bound on a binding region of the flexible display panel. The chip on film has at least two rows of output pads and the flexible display panel has at least two rows of input pads. Virtual elongation lines of all of the output pads intersect at a same intersection point in a first datum line perpendicular to the first direction. The output pads are electrically connected to the input pads and the output pads and the input pads have the virtual elongation lines at a same angle with respect to a common datum line, the common datum line being composed of the first datum line and the second datum line coinciding with each other.

公开(公告)号：US20180033753A1

公开(公告)日：2018-02-01

申请号：US15225550

申请日：2016-08-01

申请人： Xilinx, Inc.

发明人： Rafael C. Camarota

IPC分类号： H01L23/00 ,  H01L23/498

CPC分类号： H01L24/09 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5286 ,  H01L24/17 ,  H01L24/83 ,  H01L2224/0903 ,  H01L2224/0912 ,  H01L2224/1712

摘要： Methods and apparatus are described for strategically arranging conductive elements (e.g., solder balls) of an integrated circuit (IC) package (and the corresponding conductive pads of a circuit board for electrical connection with the IC package) using a plurality of different pitches. One example integrated circuit (IC) package generally includes an integrated circuit die and an arrangement of electrically conductive elements coupled to the integrated circuit die. In at least one region of the arrangement, the conductive elements are disposed with a first pitch in a first dimension of the arrangement and with a second pitch in a second dimension of the arrangement, and the second pitch is different from the first pitch. The pitch of a given region may be based on mechanical, PCB routing, and/or signal integrity considerations.

公开(公告)号：US20170186733A1

公开(公告)日：2017-06-29

申请号：US15457744

申请日：2017-03-13

申请人： IMEC VZW ,  Katholieke Universiteit Leuven, KU LEUVEN R&D

发明人： Vikas Dubey ,  Ingrid De Wolf ,  Eric Beyne

IPC分类号： H01L25/065 ,  H01L25/00 ,  H01L23/31 ,  H01L23/00 ,  H01L23/528

CPC分类号： H01L25/0657 ,  H01L23/3157 ,  H01L23/3192 ,  H01L23/528 ,  H01L24/02 ,  H01L24/05 ,  H01L24/08 ,  H01L24/09 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/33 ,  H01L24/80 ,  H01L24/81 ,  H01L24/83 ,  H01L25/50 ,  H01L2224/0213 ,  H01L2224/0214 ,  H01L2224/02145 ,  H01L2224/0217 ,  H01L2224/02175 ,  H01L2224/0218 ,  H01L2224/02185 ,  H01L2224/0224 ,  H01L2224/0225 ,  H01L2224/02255 ,  H01L2224/0401 ,  H01L2224/05647 ,  H01L2224/08145 ,  H01L2224/08225 ,  H01L2224/0903 ,  H01L2224/10135 ,  H01L2224/10145 ,  H01L2224/10165 ,  H01L2224/10175 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16147 ,  H01L2224/16148 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/1703 ,  H01L2224/80004 ,  H01L2224/80007 ,  H01L2224/80121 ,  H01L2224/8013 ,  H01L2224/80132 ,  H01L2224/80143 ,  H01L2224/80203 ,  H01L2224/80894 ,  H01L2224/80907 ,  H01L2224/81002 ,  H01L2224/81007 ,  H01L2224/81121 ,  H01L2224/8113 ,  H01L2224/81132 ,  H01L2224/81141 ,  H01L2224/81143 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/81894 ,  H01L2224/81907 ,  H01L2224/83143 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06593 ,  H01L2924/14 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/00014

摘要： Alignment of a first micro-electronic component to a receiving surface of a second micro-electronic component is realized by a capillary force-induced self-alignment, combined with an electrostatic alignment. The latter is accomplished by providing at least one first electrical conductor line along the periphery of the first component, and at least one second electrical conductor along the periphery of the location on the receiving surface of the second component onto which the component is to be placed. The contact areas surrounded by the conductor lines are covered with a wetting layer. The electrical conductor lines may be embedded in a strip of anti-wetting material that runs along the peripheries to create a wettability contrast. The wettability contrast helps to maintain a drop of alignment liquid between the contact areas so as to obtain self-alignment by capillary force. By applying appropriate charges on the conductor lines, electrostatic self-alignment is realized, which improves the alignment obtained through capillary force and maintains the alignment during evaporation of the liquid.