公开(公告)号：US09893047B2

公开(公告)日：2018-02-13

申请号：US15490377

申请日：2017-04-18

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Bing Dang ,  John Knickerbocker

IPC: H01L21/66 ,  H01L25/00 ,  H01L25/065 ,  H01L23/00 ,  H01L21/78 ,  H01L21/56 ,  H01L21/683 ,  H01L25/16 ,  H01L25/18 ,  H01L25/075 ,  H01L25/11 ,  H01L25/04 ,  H01L25/07

CPC classification number: H01L25/50 ,  H01L21/561 ,  H01L21/563 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/78 ,  H01L22/20 ,  H01L24/32 ,  H01L24/81 ,  H01L24/95 ,  H01L24/96 ,  H01L24/97 ,  H01L25/043 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/074 ,  H01L25/0756 ,  H01L25/117 ,  H01L25/167 ,  H01L25/18 ,  H01L2221/68322 ,  H01L2221/68327 ,  H01L2221/68359 ,  H01L2221/68363 ,  H01L2221/68381 ,  H01L2223/6677 ,  H01L2224/14181 ,  H01L2224/16146 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/80121 ,  H01L2224/80143 ,  H01L2224/81005 ,  H01L2224/95001 ,  H01L2224/95144 ,  H01L2224/95146 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014

Abstract: Disclosed is a process, structure, equipment and apparatus directed to a low cost, high volume approach for the assembly of ultra small die to three-dimensional (3D) or 2.5D semiconductor packages.

公开(公告)号：US20170221872A1

公开(公告)日：2017-08-03

申请号：US15490377

申请日：2017-04-18

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Bing Dang ,  John Knickerbocker

IPC: H01L25/00 ,  H01L21/66 ,  H01L21/78 ,  H01L25/18 ,  H01L25/16 ,  H01L23/00 ,  H01L21/683 ,  H01L21/56

CPC classification number: H01L25/50 ,  H01L21/561 ,  H01L21/563 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/78 ,  H01L22/20 ,  H01L24/32 ,  H01L24/81 ,  H01L24/95 ,  H01L24/96 ,  H01L24/97 ,  H01L25/043 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/074 ,  H01L25/0756 ,  H01L25/117 ,  H01L25/167 ,  H01L25/18 ,  H01L2221/68322 ,  H01L2221/68327 ,  H01L2221/68359 ,  H01L2221/68363 ,  H01L2221/68381 ,  H01L2223/6677 ,  H01L2224/14181 ,  H01L2224/16146 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/80121 ,  H01L2224/80143 ,  H01L2224/81005 ,  H01L2224/95001 ,  H01L2224/95144 ,  H01L2224/95146 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014

Abstract: Disclosed is a process, structure, equipment and apparatus directed to a low cost, high volume approach for the assembly of ultra small die to three-dimensional (3D) or 2.5D semiconductor packages.

公开(公告)号：US20130252375A1

公开(公告)日：2013-09-26

申请号：US13429440

申请日：2012-03-26

Applicant: Ge Yi ,  Zongrong Liu ,  Yunjun Tang ,  Shaoping Li

Inventor： Ge Yi ,  Zongrong Liu ,  Yunjun Tang ,  Shaoping Li

IPC: H01L23/00

CPC classification number: H01L24/83 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/80 ,  H01L24/81 ,  H01L24/94 ,  H01L24/97 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03612 ,  H01L2224/03614 ,  H01L2224/0362 ,  H01L2224/03826 ,  H01L2224/03827 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05084 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05157 ,  H01L2224/05547 ,  H01L2224/05576 ,  H01L2224/05578 ,  H01L2224/056 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/08146 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/11462 ,  H01L2224/1162 ,  H01L2224/13022 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/16146 ,  H01L2224/80121 ,  H01L2224/80143 ,  H01L2224/80169 ,  H01L2224/80801 ,  H01L2224/81121 ,  H01L2224/81143 ,  H01L2224/81169 ,  H01L2224/81801 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/01322 ,  H01L2924/1461 ,  H01L2924/00015 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/01026 ,  H01L2924/01028 ,  H01L2924/01078 ,  H01L2924/01024 ,  H01L2224/80 ,  H01L2224/81 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/00

Abstract: A high-precision alignment method with high throughput is proposed, which can be used for wafer-to-wafer, chip-to-wafer or chip-to-chip bonding. The scheme implements pairing patterned magnets predetermined designed and made using wafer level process on two components (wafer or chip). The magnetization in patterned magnet can be set at predetermined configuration before bonding starts. When, the two components are bought to close proximity after a coarse alignment, the magnetic force will bring the magnet pairs together and aligned the patterned magnet on one component with its mirrored or complimentary patterned magnets on the other component to minimize the overall the magnetic energy of the pairing magnet. A few patterned magnet structures and materials, with their unique merits are proposed as examples for magnet pair for the self-alignment purpose. This method enables solid contact at the bonding interface via patterned magnets under the magnetic force, which avoid the wafer drafting due to the formation of the liquid phases.

Abstract translation: 提出了一种高精度的高通量对准方法，可用于晶圆到晶圆，晶片到晶圆或芯片间的接合。 该方案实现了使用晶片级处理在两个部件（晶片或芯片）上预先设计和制造的配对图案化磁体。 在接合开始之前，图案化磁体中的磁化可以被设定为预定的配置。 当两个部件在粗对准之后被购买成靠近时，磁力将使磁体对在一起，并将其上的图案化磁体与其另一部件上的镜像或互补的图案化磁体对准，以最小化整个磁能 的配对磁铁。 提出了一些具有独特优点的图案化磁体结构和材料作为用于自对准目的的磁体对的示例。 该方法能够在磁力下通过图案化的磁体在接合界面处实现牢固的接触，从而避免由于液相的形成引起的晶片牵伸。

公开(公告)号：US12009338B2

公开(公告)日：2024-06-11

申请号：US17206725

申请日：2021-03-19

Applicant: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.

Inventor： Guilian Gao ,  Laura Wills Mirkarimi ,  Gaius Gillman Fountain, Jr. ,  Cyprian Emeka Uzoh

IPC: H01L23/00

CPC classification number: H01L24/80 ,  H01L24/08 ,  H01L2224/08145 ,  H01L2224/80031 ,  H01L2224/80143 ,  H01L2224/80895 ,  H01L2224/80896

Abstract: A method of direct hybrid bonding first and second semiconductor elements of differential thickness is disclosed. The method can include patterning a plurality of first contact features on the first semiconductor element. The method can include second a plurality of second contact features on the second semiconductor element corresponding to the first contact features for direct hybrid bonding. The method can include applying a lithographic magnification correction factor to one of the first patterning and second patterning without applying the lithographic magnification correction factor to the other of the first patterning and the second patterning. In various embodiments, a differential expansion compensation structure can be disposed on at least one of the first and the second semiconductor elements. The differential expansion compensation structure can be configured to compensate for differential expansion between the first and second semiconductor elements to reduce misalignment between at least the second and fourth contact features.

公开(公告)号：US20170186733A1

公开(公告)日：2017-06-29

申请号：US15457744

申请日：2017-03-13

Applicant: IMEC VZW ,  Katholieke Universiteit Leuven, KU LEUVEN R&D

Inventor： Vikas Dubey ,  Ingrid De Wolf ,  Eric Beyne

IPC: H01L25/065 ,  H01L25/00 ,  H01L23/31 ,  H01L23/00 ,  H01L23/528

CPC classification number: H01L25/0657 ,  H01L23/3157 ,  H01L23/3192 ,  H01L23/528 ,  H01L24/02 ,  H01L24/05 ,  H01L24/08 ,  H01L24/09 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/33 ,  H01L24/80 ,  H01L24/81 ,  H01L24/83 ,  H01L25/50 ,  H01L2224/0213 ,  H01L2224/0214 ,  H01L2224/02145 ,  H01L2224/0217 ,  H01L2224/02175 ,  H01L2224/0218 ,  H01L2224/02185 ,  H01L2224/0224 ,  H01L2224/0225 ,  H01L2224/02255 ,  H01L2224/0401 ,  H01L2224/05647 ,  H01L2224/08145 ,  H01L2224/08225 ,  H01L2224/0903 ,  H01L2224/10135 ,  H01L2224/10145 ,  H01L2224/10165 ,  H01L2224/10175 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16147 ,  H01L2224/16148 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/1703 ,  H01L2224/80004 ,  H01L2224/80007 ,  H01L2224/80121 ,  H01L2224/8013 ,  H01L2224/80132 ,  H01L2224/80143 ,  H01L2224/80203 ,  H01L2224/80894 ,  H01L2224/80907 ,  H01L2224/81002 ,  H01L2224/81007 ,  H01L2224/81121 ,  H01L2224/8113 ,  H01L2224/81132 ,  H01L2224/81141 ,  H01L2224/81143 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/81894 ,  H01L2224/81907 ,  H01L2224/83143 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06593 ,  H01L2924/14 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: Alignment of a first micro-electronic component to a receiving surface of a second micro-electronic component is realized by a capillary force-induced self-alignment, combined with an electrostatic alignment. The latter is accomplished by providing at least one first electrical conductor line along the periphery of the first component, and at least one second electrical conductor along the periphery of the location on the receiving surface of the second component onto which the component is to be placed. The contact areas surrounded by the conductor lines are covered with a wetting layer. The electrical conductor lines may be embedded in a strip of anti-wetting material that runs along the peripheries to create a wettability contrast. The wettability contrast helps to maintain a drop of alignment liquid between the contact areas so as to obtain self-alignment by capillary force. By applying appropriate charges on the conductor lines, electrostatic self-alignment is realized, which improves the alignment obtained through capillary force and maintains the alignment during evaporation of the liquid.

公开(公告)号：US20170179096A1

公开(公告)日：2017-06-22

申请号：US14977068

申请日：2015-12-21

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Bing Dang ,  John Knickerbocker

IPC: H01L25/00 ,  H01L21/66 ,  H01L21/683 ,  H01L21/78 ,  H01L21/56 ,  H01L25/065 ,  H01L23/00

CPC classification number: H01L25/50 ,  H01L21/561 ,  H01L21/563 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/78 ,  H01L22/20 ,  H01L24/32 ,  H01L24/81 ,  H01L24/95 ,  H01L24/96 ,  H01L24/97 ,  H01L25/043 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/074 ,  H01L25/0756 ,  H01L25/117 ,  H01L25/167 ,  H01L25/18 ,  H01L2221/68322 ,  H01L2221/68327 ,  H01L2221/68359 ,  H01L2221/68363 ,  H01L2221/68381 ,  H01L2223/6677 ,  H01L2224/14181 ,  H01L2224/16146 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/80121 ,  H01L2224/80143 ,  H01L2224/81005 ,  H01L2224/95001 ,  H01L2224/95144 ,  H01L2224/95146 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014

Abstract: Disclosed is a process, structure, equipment and apparatus directed to a low cost, high volume approach for the assembly of ultra small die to three-dimensional (3D) or 2.5 D semiconductor packages.

公开(公告)号：US20150048523A1

公开(公告)日：2015-02-19

申请号：US14397038

申请日：2013-04-24

Applicant: Tadatomo SUGA ,  BONDTECH CO., LTD.

Inventor： Tadatomo Suga ,  Akira Yamauchi

IPC: H01L25/065 ,  B23K31/02 ,  H01L21/66 ,  H01L23/00 ,  H01L25/00 ,  H01L25/10 ,  B23K37/04 ,  B23K37/00

CPC classification number: H01L25/0652 ,  B23K31/02 ,  B23K37/00 ,  B23K37/0408 ,  B23K2101/40 ,  H01L21/6836 ,  H01L22/10 ,  H01L23/10 ,  H01L23/562 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/09 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/73 ,  H01L24/74 ,  H01L24/742 ,  H01L24/743 ,  H01L24/75 ,  H01L24/80 ,  H01L24/81 ,  H01L24/83 ,  H01L24/94 ,  H01L24/95 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2224/0384 ,  H01L2224/03845 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05611 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/06134 ,  H01L2224/0615 ,  H01L2224/06177 ,  H01L2224/08145 ,  H01L2224/08225 ,  H01L2224/09181 ,  H01L2224/1184 ,  H01L2224/11845 ,  H01L2224/13009 ,  H01L2224/13016 ,  H01L2224/13017 ,  H01L2224/13021 ,  H01L2224/13022 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/14134 ,  H01L2224/1415 ,  H01L2224/14177 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/27009 ,  H01L2224/2755 ,  H01L2224/27823 ,  H01L2224/2784 ,  H01L2224/27845 ,  H01L2224/29111 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/73103 ,  H01L2224/74 ,  H01L2224/7501 ,  H01L2224/75101 ,  H01L2224/75102 ,  H01L2224/7525 ,  H01L2224/75251 ,  H01L2224/75252 ,  H01L2224/75283 ,  H01L2224/753 ,  H01L2224/75301 ,  H01L2224/7531 ,  H01L2224/75501 ,  H01L2224/75502 ,  H01L2224/7565 ,  H01L2224/75701 ,  H01L2224/75702 ,  H01L2224/75753 ,  H01L2224/75802 ,  H01L2224/75804 ,  H01L2224/75824 ,  H01L2224/75842 ,  H01L2224/7598 ,  H01L2224/80003 ,  H01L2224/8001 ,  H01L2224/80013 ,  H01L2224/80065 ,  H01L2224/8013 ,  H01L2224/80132 ,  H01L2224/80143 ,  H01L2224/80201 ,  H01L2224/80203 ,  H01L2224/8022 ,  H01L2224/8023 ,  H01L2224/80447 ,  H01L2224/8083 ,  H01L2224/80907 ,  H01L2224/81002 ,  H01L2224/8101 ,  H01L2224/81013 ,  H01L2224/81065 ,  H01L2224/8113 ,  H01L2224/81132 ,  H01L2224/81143 ,  H01L2224/81193 ,  H01L2224/81201 ,  H01L2224/81203 ,  H01L2224/8122 ,  H01L2224/8123 ,  H01L2224/81447 ,  H01L2224/81801 ,  H01L2224/81805 ,  H01L2224/8183 ,  H01L2224/81907 ,  H01L2224/83002 ,  H01L2224/8301 ,  H01L2224/83013 ,  H01L2224/83048 ,  H01L2224/83051 ,  H01L2224/83065 ,  H01L2224/83091 ,  H01L2224/8313 ,  H01L2224/83132 ,  H01L2224/83136 ,  H01L2224/83143 ,  H01L2224/83193 ,  H01L2224/83201 ,  H01L2224/83203 ,  H01L2224/8322 ,  H01L2224/8323 ,  H01L2224/83234 ,  H01L2224/83355 ,  H01L2224/83447 ,  H01L2224/83801 ,  H01L2224/8383 ,  H01L2224/83894 ,  H01L2224/83907 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06565 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01322 ,  H01L2924/10157 ,  H01L2924/10253 ,  H01L2924/3511 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2224/80 ,  H01L2224/83 ,  H01L2924/00

Abstract: [Problem] Provided is a technique for bonding chips efficiently onto a wafer to establish an electrical connection and raise mechanical strength between the chips and the wafer or between the chips that are chips laminated onto each other in the state that resin and other undesired residues do not remain on a bond interface therebetween.[Solution] A method for bonding plural chips each having a chip-side-bond-surface having metal regions to a substrate having plural bond portions has the step (S1) of subjecting the metal regions of the chip-side-bond-surface to surface activating treatment and hydrophilizing treatment; the step (S2) of subjecting the bond portions of the substrate to surface activating treatment and hydrophilizing treatment; the step (S3) of fitting the chips subjected to the surface activating treatment and the hydrophilizing treatment onto the corresponding bond portions of the substrate subjected to the surface activating treatment and the hydrophilizing treatment to bring the metal regions of the chips into contact with the bond portions of the substrate; and the step (S4) of heating the resultant structure, which includes the substrate, and the chips fitted onto the substrate.

Abstract translation: [问题]提供了一种将芯片有效地接合到晶片上以建立电连接并提高芯片和晶片之间或芯片之间的机械强度的技术，该芯片是在树脂和其它不期望的残留物的状态下彼此层压的芯片 不保留在它们之间的结合界面上。 [解决方案]将具有金属区域的具有芯片侧接合面的多个芯片接合到具有多个结合部的基板的方法具有将芯片侧接合面的金属区域 表面活化处理和亲水处理; 对所述基板的所述接合部进行表面活化处理和亲水化处理的工序（S2） 将经过表面活化处理和亲水化处理的芯片装配到经过表面活化处理的基板的相应接合部分和亲水化处理上以使芯片的金属区域与键接触的步骤（S3） 基板的一部分; 以及加热包括基板的所得结构和安装在基板上的芯片的步骤（S4）。

公开(公告)号：US20240312953A1

公开(公告)日：2024-09-19

申请号：US18671851

申请日：2024-05-22

Applicant: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.

Inventor： Guilian Gao ,  Laura Wills Mirkarimi ,  Gaius Gillman Fountain, JR. ,  Cyprian Emeka Uzoh

IPC: H01L23/00

CPC classification number: H01L24/80 ,  H01L24/08 ,  H01L2224/08145 ,  H01L2224/80031 ,  H01L2224/80143 ,  H01L2224/80895 ,  H01L2224/80896

Abstract: A method of direct hybrid bonding first and second semiconductor elements of differential thickness is disclosed. The method can include patterning a plurality of first contact features on the first semiconductor element. The method can include second a plurality of second contact features on the second semiconductor element corresponding to the first contact features for direct hybrid bonding. The method can include applying a lithographic magnification correction factor to one of the first patterning and second patterning without applying the lithographic magnification correction factor to the other of the first patterning and the second patterning. In various embodiments, a differential expansion compensation structure can be disposed on at least one of the first and the second semiconductor elements. The differential expansion compensation structure can be configured to compensate for differential expansion between the first and second semiconductor elements to reduce misalignment between at least the second and fourth contact features.

公开(公告)号：US09806057B2

公开(公告)日：2017-10-31

申请号：US14643831

申请日：2015-03-10

Applicant: DISCO CORPORATION

Inventor： Kazuma Sekiya

IPC: H01L21/00 ,  H01L23/00 ,  H01L21/683

CPC classification number: H01L24/97 ,  H01L21/6835 ,  H01L24/08 ,  H01L24/19 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/80 ,  H01L24/83 ,  H01L24/95 ,  H01L2221/68359 ,  H01L2221/68368 ,  H01L2224/08225 ,  H01L2224/26175 ,  H01L2224/27013 ,  H01L2224/27334 ,  H01L2224/29194 ,  H01L2224/32225 ,  H01L2224/80143 ,  H01L2224/80385 ,  H01L2224/80904 ,  H01L2224/80907 ,  H01L2224/83002 ,  H01L2224/83143 ,  H01L2224/83192 ,  H01L2224/83385 ,  H01L2224/8385 ,  H01L2224/83907 ,  H01L2224/9205 ,  H01L2224/95 ,  H01L2224/95146 ,  H01L2224/97 ,  H01L2924/12042 ,  H01L2924/00 ,  H01L2224/83 ,  H01L2224/80 ,  H01L2924/00014 ,  H01L2224/19

Abstract: A chip arranging method for arranging a plurality of chips on a wafer includes a groove forming step of forming a plurality of intersecting grooves that mark off each of chip placement regions on the front surface side of the wafer, a liquid supplying step of supplying a liquid to the chip placement regions, a chip placing step of placing the chips on the liquid to position the chips in the chip placement regions by the surface tension of the liquid after carrying out the liquid supplying step, and a liquid removing step of removing the liquid to arrange the plurality of chips on the wafer after carrying out the chip placing step.

公开(公告)号：US09691747B1

公开(公告)日：2017-06-27

申请号：US14977068

申请日：2015-12-21

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Bing Dang ,  John Knickerbocker

IPC: H01L21/78 ,  H01L25/00 ,  H01L25/065 ,  H01L21/66 ,  H01L23/00 ,  H01L21/56 ,  H01L21/683 ,  H01L25/075 ,  H01L25/11 ,  H01L25/04 ,  H01L25/07

CPC classification number: H01L25/50 ,  H01L21/561 ,  H01L21/563 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/78 ,  H01L22/20 ,  H01L24/32 ,  H01L24/81 ,  H01L24/95 ,  H01L24/96 ,  H01L24/97 ,  H01L25/043 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/074 ,  H01L25/0756 ,  H01L25/117 ,  H01L25/167 ,  H01L25/18 ,  H01L2221/68322 ,  H01L2221/68327 ,  H01L2221/68359 ,  H01L2221/68363 ,  H01L2221/68381 ,  H01L2223/6677 ,  H01L2224/14181 ,  H01L2224/16146 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/80121 ,  H01L2224/80143 ,  H01L2224/81005 ,  H01L2224/95001 ,  H01L2224/95144 ,  H01L2224/95146 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014

Abstract: Disclosed is a process, structure, equipment and apparatus directed to a low cost, high volume approach for the assembly of ultra small die to three-dimensional (3D) or 2.5D semiconductor packages.