公开(公告)号：US20230207611A1

公开(公告)日：2023-06-29

申请号：US18177613

申请日：2023-03-02

Applicant: VueReal Inc.

Inventor： Gholamreza Chaji ,  Ehsanollah Fathi

IPC: H01L27/15 ,  H01L33/40 ,  H01L33/58 ,  H01L33/00 ,  H01L23/00 ,  H01L21/683 ,  H01L25/16 ,  H01L25/075

CPC classification number: H01L27/156 ,  H01L33/405 ,  H01L33/58 ,  H01L33/005 ,  H01L24/97 ,  H01L24/96 ,  H01L24/05 ,  H01L21/6835 ,  H01L24/13 ,  H01L24/24 ,  H01L25/167 ,  H01L24/92 ,  H01L25/0753 ,  H01L2933/0058 ,  H01L2933/0016 ,  H01L2224/96 ,  H01L2224/83002 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/97 ,  H01L2224/83005 ,  H01L2224/32235 ,  H01L24/08 ,  H01L2224/24137 ,  H01L2224/83907 ,  H01L24/83 ,  H01L2224/81385 ,  H01L2224/80907 ,  H01L2224/16237 ,  H01L2224/80004 ,  H01L24/16 ,  H01L2224/08225 ,  H01L2224/80385 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L24/80 ,  H01L2224/92 ,  H01L24/32 ,  H01L2224/80006 ,  H01L2224/0401 ,  H01L2221/68322 ,  H01L2224/9202 ,  H01L2221/68354 ,  H01L2221/68363 ,  H01L2221/68381 ,  H01L2224/83385 ,  H01L33/44

Abstract: This disclosure is related to post processing steps for integrating of micro devices into system (receiver) substrate or improving the performance of the micro devices after transfer. Post processing steps for additional structure such as reflective layers, fillers, black matrix or other layers may be used to improve the out coupling or confining of the generated LED light. In another example, dielectric and metallic layers may be used to integrate an electro-optical thin film device into the system substrate with the transferred micro devices. In another example, color conversion layers are integrated into the system substrate to create different output from the micro devices.

公开(公告)号：US09379006B2

公开(公告)日：2016-06-28

申请号：US14162140

申请日：2014-01-23

Applicant: Sony Corporation

Inventor： Yoshihisa Kagawa ,  Naoki Komai

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/00

CPC classification number: H01L21/76838 ,  H01L23/53209 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/80 ,  H01L24/94 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03505 ,  H01L2224/03616 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05186 ,  H01L2224/05546 ,  H01L2224/05547 ,  H01L2224/05571 ,  H01L2224/05647 ,  H01L2224/08147 ,  H01L2224/0903 ,  H01L2224/45147 ,  H01L2224/48847 ,  H01L2224/80004 ,  H01L2224/80011 ,  H01L2224/80075 ,  H01L2224/8009 ,  H01L2224/80092 ,  H01L2224/80357 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2225/06541 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01012 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/12043 ,  H01L2924/13091 ,  H01L2924/1434 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/48 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2224/05552 ,  H01L2924/01005 ,  H01L2924/01004 ,  H01L2924/01033

Abstract: A semiconductor apparatus, electronic device, and method of manufacturing the semiconductor apparatus are disclosed. In one example, the semiconductor apparatus comprises a first semiconductor part that includes a first wiring, and a second semiconductor part that is adhered to the first semiconductor part and which includes a second wiring electrically connected to the first wiring. A metallic oxide is formed in at least one of the first wiring and the second wiring.

Abstract translation: 公开了一种半导体装置，电子装置和半导体装置的制造方法。 在一个示例中，半导体装置包括第一半导体部分，其包括第一布线，第二半导体部分粘附到第一半导体部分，并且包括电连接到第一布线的第二布线。 金属氧化物形成在第一布线和第二布线中的至少一个中。

公开(公告)号：US20150311179A1

公开(公告)日：2015-10-29

申请号：US14795579

申请日：2015-07-09

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： CHENG-WEI CHENG ,  SHU-JEN HAN ,  MASAHARU KOBAYASHI ,  KO-TAO LEE ,  DEVENDRA K. SADANA ,  KUEN-TING SHIU

IPC: H01L23/00 ,  H01L21/02

CPC classification number: H01L24/89 ,  H01L21/02381 ,  H01L21/02389 ,  H01L21/6835 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/80 ,  H01L24/92 ,  H01L29/78603 ,  H01L29/78681 ,  H01L2221/68363 ,  H01L2221/68377 ,  H01L2221/68381 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0361 ,  H01L2224/03914 ,  H01L2224/05617 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/08145 ,  H01L2224/08225 ,  H01L2224/08245 ,  H01L2224/80004 ,  H01L2224/80006 ,  H01L2224/80052 ,  H01L2224/80201 ,  H01L2224/80203 ,  H01L2224/80379 ,  H01L2224/80801 ,  H01L2224/8083 ,  H01L2224/80894 ,  H01L2224/9202 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/01032 ,  H01L2224/03 ,  H01L2924/00

Abstract: A device and method for fabrication includes providing a first substrate assembly including a first substrate and a first metal layer formed on the first substrate and a second substrate assembly including a second substrate and a second metal layer formed on the second substrate. The first metal layer is joined to the second metal layer using a cold welding process wherein one of the first substrate and the second substrate includes a semiconductor channel layer for forming a transistor device.

Abstract translation: 一种用于制造的器件和方法，包括提供包括第一衬底和形成在第一衬底上的第一金属层的第一衬底组件和包括形成在第二衬底上的第二衬底和第二金属层的第二衬底组件。 使用冷焊工艺将第一金属层接合到第二金属层，其中第一基板和第二基板中的一个包括用于形成晶体管器件的半导体沟道层。

公开(公告)号：US09048283B2

公开(公告)日：2015-06-02

申请号：US13542507

申请日：2012-07-05

Applicant: Ping-Yin Liu ,  Shih-Wei Lin ,  Xin-Hua Huang ,  Lan-Lin Chao ,  Chia-Shiung Tsai

Inventor： Ping-Yin Liu ,  Shih-Wei Lin ,  Xin-Hua Huang ,  Lan-Lin Chao ,  Chia-Shiung Tsai

IPC: H01L21/30 ,  H01L23/00

CPC classification number: H01L24/80 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/27 ,  H01L24/74 ,  H01L24/94 ,  H01L2224/02215 ,  H01L2224/0361 ,  H01L2224/03616 ,  H01L2224/0381 ,  H01L2224/05647 ,  H01L2224/05687 ,  H01L2224/08145 ,  H01L2224/74 ,  H01L2224/7501 ,  H01L2224/75101 ,  H01L2224/7565 ,  H01L2224/75753 ,  H01L2224/75824 ,  H01L2224/80004 ,  H01L2224/80007 ,  H01L2224/8001 ,  H01L2224/80011 ,  H01L2224/80013 ,  H01L2224/80014 ,  H01L2224/80065 ,  H01L2224/80075 ,  H01L2224/80097 ,  H01L2224/80121 ,  H01L2224/80136 ,  H01L2224/80203 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/83889 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/1461 ,  H01L2924/351 ,  Y10T156/15 ,  Y10T156/1744 ,  H01L2924/00012 ,  H01L2224/80 ,  H01L2924/05442 ,  H01L2924/00

Abstract: Hybrid bonding systems and methods for semiconductor wafers are disclosed. In one embodiment, a hybrid bonding system for semiconductor wafers includes a chamber and a plurality of sub-chambers disposed within the chamber. A robotics handler is disposed within the chamber that is adapted to move a plurality of semiconductor wafers within the chamber between the plurality of sub-chambers. The plurality of sub-chambers includes a first sub-chamber adapted to remove a protection layer from the plurality of semiconductor wafers, and a second sub-chamber adapted to activate top surfaces of the plurality of semiconductor wafers prior to hybrid bonding the plurality of semiconductor wafers together. The plurality of sub-chambers also includes a third sub-chamber adapted to align the plurality of semiconductor wafers and hybrid bond the plurality of semiconductor wafers together.

Abstract translation: 公开了用于半导体晶片的混合键合系统和方法。 在一个实施例中，用于半导体晶片的混合键合系统包括腔室和设置在腔室内的多个子腔室。 机器人处理器设置在腔室内，其适于移动多个子室内的室内的多个半导体晶片。 多个子室包括适于从多个半导体晶片去除保护层的第一子室，以及适于在混合结合多个半导体之前激活多个半导体晶片的顶表面的第二子室 晶圆在一起 多个子室还包括适于对准多个半导体晶片并将多个半导体晶片混合地结合在一起的第三子室。

公开(公告)号：US20140091370A1

公开(公告)日：2014-04-03

申请号：US13660497

申请日：2012-10-25

Applicant: INTERNATIONAL BUSINESS MACHINES CORP

Inventor： CHENG-WEI CHENG ,  SHU-JEN HAN ,  MASAHARU KOBAYASHI ,  KO-TAO LEE ,  DEVENDRA K. SADANA ,  KUEN-TING SHIU

IPC: H01L29/78 ,  H01L23/48

CPC classification number: H01L24/89 ,  H01L21/02381 ,  H01L21/02389 ,  H01L21/6835 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/80 ,  H01L24/92 ,  H01L29/78603 ,  H01L29/78681 ,  H01L2221/68363 ,  H01L2221/68377 ,  H01L2221/68381 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0361 ,  H01L2224/03914 ,  H01L2224/05617 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/08145 ,  H01L2224/08225 ,  H01L2224/08245 ,  H01L2224/80004 ,  H01L2224/80006 ,  H01L2224/80052 ,  H01L2224/80201 ,  H01L2224/80203 ,  H01L2224/80379 ,  H01L2224/80801 ,  H01L2224/8083 ,  H01L2224/80894 ,  H01L2224/9202 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/01032 ,  H01L2224/03 ,  H01L2924/00

Abstract: A device and method for fabrication includes providing a first substrate assembly including a first substrate and a first metal layer formed on the first substrate and a second substrate assembly including a second substrate and a second metal layer formed on the second substrate. The first metal layer is joined to the second metal layer using a cold welding process wherein one of the first substrate and the second substrate includes a semiconductor channel layer for forming a transistor device.

Abstract translation: 一种用于制造的器件和方法，包括提供包括第一衬底和形成在第一衬底上的第一金属层的第一衬底组件和包括形成在第二衬底上的第二衬底和第二金属层的第二衬底组件。 使用冷焊工艺将第一金属层接合到第二金属层，其中第一基板和第二基板中的一个包括用于形成晶体管器件的半导体沟道层。

公开(公告)号：US20120241961A1

公开(公告)日：2012-09-27

申请号：US13416412

申请日：2012-03-09

Applicant: Yoshihisa Kagawa ,  Naoki Komai

Inventor： Yoshihisa Kagawa ,  Naoki Komai

IPC: H01L23/522 ,  H01L21/768

CPC classification number: H01L21/76838 ,  H01L23/53209 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/80 ,  H01L24/94 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03505 ,  H01L2224/03616 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05186 ,  H01L2224/05546 ,  H01L2224/05547 ,  H01L2224/05571 ,  H01L2224/05647 ,  H01L2224/08147 ,  H01L2224/0903 ,  H01L2224/45147 ,  H01L2224/48847 ,  H01L2224/80004 ,  H01L2224/80011 ,  H01L2224/80075 ,  H01L2224/8009 ,  H01L2224/80092 ,  H01L2224/80357 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2225/06541 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01012 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/12043 ,  H01L2924/13091 ,  H01L2924/1434 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/48 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2224/05552 ,  H01L2924/01005 ,  H01L2924/01004 ,  H01L2924/01033

Abstract: Disclosed herein is a semiconductor apparatus including: a first semiconductor part including a first wiring; a second semiconductor part which is adhered to the first semiconductor part and which includes a second wiring electrically connected to the first wiring; and a metallic oxide formed by a reaction between oxygen and a metallic material which reacts with oxygen more easily than hydrogen does, the metallic oxide having been diffused into a region which includes a joint interface between the first wiring and the second wiring and the inside of at least one of the first wiring and the second wiring.

Abstract translation: 本发明公开了一种半导体装置，包括：第一半导体部件，包括第一布线; 第二半导体部分，其粘附到第一半导体部分，并且包括电连接到第一布线的第二布线; 以及通过氧与金之间的反应比金更容易地与氧反应形成的金属氧化物，所述金属氧化物已经扩散到包括第一布线和第二布线之间的接合界面的区域中，以及内部 第一布线和第二布线中的至少一个。

公开(公告)号：US11894335B2

公开(公告)日：2024-02-06

申请号：US17337626

申请日：2021-06-03

Applicant: Japan Display Inc.

Inventor： Kazuyuki Yamada ,  Keisuke Asada ,  Kenichi Takemasa

IPC: H01L33/62 ,  H01L25/16 ,  H01L23/00

CPC classification number: H01L24/80 ,  H01L24/08 ,  H01L25/167 ,  H01L33/62 ,  H01L24/05 ,  H01L2224/05611 ,  H01L2224/05644 ,  H01L2224/08145 ,  H01L2224/08502 ,  H01L2224/80004 ,  H01L2224/80024 ,  H01L2224/8085 ,  H01L2224/80224 ,  H01L2224/80805 ,  H01L2224/80907 ,  H01L2924/12041 ,  H01L2924/1426

Abstract: A method for manufacturing a display device includes preparing a circuit board including a drive circuit for driving a LED chip, forming a connecting electrode on the circuit board, forming an adhesive layer on the connecting electrode, adhering a terminal electrode of the LED chip on the adhesive layer and joining the connecting electrode and the terminal electrode by irradiating a laser light. The adhesive layer may be formed only on a upper surface of the connecting electrode.

公开(公告)号：US09799632B2

公开(公告)日：2017-10-24

申请号：US15457744

申请日：2017-03-13

Applicant: IMEC VZW ,  Katholieke Universiteit Leuven, KU LEUVEN R&D

Inventor： Vikas Dubey ,  Ingrid De Wolf ,  Eric Beyne

IPC: H01L23/02 ,  H01L25/065 ,  H01L23/00 ,  H01L23/528 ,  H01L23/31 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L23/3157 ,  H01L23/3192 ,  H01L23/528 ,  H01L24/02 ,  H01L24/05 ,  H01L24/08 ,  H01L24/09 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/33 ,  H01L24/80 ,  H01L24/81 ,  H01L24/83 ,  H01L25/50 ,  H01L2224/0213 ,  H01L2224/0214 ,  H01L2224/02145 ,  H01L2224/0217 ,  H01L2224/02175 ,  H01L2224/0218 ,  H01L2224/02185 ,  H01L2224/0224 ,  H01L2224/0225 ,  H01L2224/02255 ,  H01L2224/0401 ,  H01L2224/05647 ,  H01L2224/08145 ,  H01L2224/08225 ,  H01L2224/0903 ,  H01L2224/10135 ,  H01L2224/10145 ,  H01L2224/10165 ,  H01L2224/10175 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16147 ,  H01L2224/16148 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/1703 ,  H01L2224/80004 ,  H01L2224/80007 ,  H01L2224/80121 ,  H01L2224/8013 ,  H01L2224/80132 ,  H01L2224/80143 ,  H01L2224/80203 ,  H01L2224/80894 ,  H01L2224/80907 ,  H01L2224/81002 ,  H01L2224/81007 ,  H01L2224/81121 ,  H01L2224/8113 ,  H01L2224/81132 ,  H01L2224/81141 ,  H01L2224/81143 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/81894 ,  H01L2224/81907 ,  H01L2224/83143 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06593 ,  H01L2924/14 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: Alignment of a first micro-electronic component to a receiving surface of a second micro-electronic component is realized by a capillary force-induced self-alignment, combined with an electrostatic alignment. The latter is accomplished by providing at least one first electrical conductor line along the periphery of the first component, and at least one second electrical conductor along the periphery of the location on the receiving surface of the second component onto which the component is to be placed. The contact areas surrounded by the conductor lines are covered with a wetting layer. The electrical conductor lines may be embedded in a strip of anti-wetting material that runs along the peripheries to create a wettability contrast. The wettability contrast helps to maintain a drop of alignment liquid between the contact areas so as to obtain self-alignment by capillary force. By applying appropriate charges on the conductor lines, electrostatic self-alignment is realized, which improves the alignment obtained through capillary force and maintains the alignment during evaporation of the liquid.

公开(公告)号：US09601459B2

公开(公告)日：2017-03-21

申请号：US14576637

申请日：2014-12-19

Applicant: IMEC VZW ,  Katholieke Universiteit Leuven, KU LEUVEN R&D

Inventor： Vikas Dubey ,  Ingrid De Wolf ,  Eric Beyne

IPC: H01L29/80 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L23/3157 ,  H01L23/3192 ,  H01L23/528 ,  H01L24/02 ,  H01L24/05 ,  H01L24/08 ,  H01L24/09 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/33 ,  H01L24/80 ,  H01L24/81 ,  H01L24/83 ,  H01L25/50 ,  H01L2224/0213 ,  H01L2224/0214 ,  H01L2224/02145 ,  H01L2224/0217 ,  H01L2224/02175 ,  H01L2224/0218 ,  H01L2224/02185 ,  H01L2224/0224 ,  H01L2224/0225 ,  H01L2224/02255 ,  H01L2224/0401 ,  H01L2224/05647 ,  H01L2224/08145 ,  H01L2224/08225 ,  H01L2224/0903 ,  H01L2224/10135 ,  H01L2224/10145 ,  H01L2224/10165 ,  H01L2224/10175 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16147 ,  H01L2224/16148 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/1703 ,  H01L2224/80004 ,  H01L2224/80007 ,  H01L2224/80121 ,  H01L2224/8013 ,  H01L2224/80132 ,  H01L2224/80143 ,  H01L2224/80203 ,  H01L2224/80894 ,  H01L2224/80907 ,  H01L2224/81002 ,  H01L2224/81007 ,  H01L2224/81121 ,  H01L2224/8113 ,  H01L2224/81132 ,  H01L2224/81141 ,  H01L2224/81143 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/81894 ,  H01L2224/81907 ,  H01L2224/83143 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06593 ,  H01L2924/14 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: Alignment of a first micro-electronic component to a receiving surface of a second micro-electronic component is realized by a capillary force-induced self-alignment, combined with an electrostatic alignment. The latter is accomplished by providing at least one first electrical conductor line along the periphery of the first component, and at least one second electrical conductor along the periphery of the location on the receiving surface of the second component onto which the component is to be placed. The contact areas surrounded by the conductor lines are covered with a wetting layer. The electrical conductor lines may be embedded in a strip of anti-wetting material that runs along the peripheries to create a wettability contrast. The wettability contrast helps to maintain a drop of alignment liquid between the contact areas so as to obtain self-alignment by capillary force. By applying appropriate charges on the conductor lines, electrostatic self-alignment is realized, which improves the alignment obtained through capillary force and maintains the alignment during evaporation of the liquid.

公开(公告)号：US20150287694A1

公开(公告)日：2015-10-08

申请号：US14725266

申请日：2015-05-29

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ping-Yin Liu ,  Shih-Wei Lin ,  Xin-Hua Huang ,  Lan-Lin Chao ,  Chia-Shiung Tsai

IPC: H01L23/00

CPC classification number: H01L24/80 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/27 ,  H01L24/74 ,  H01L24/94 ,  H01L2224/02215 ,  H01L2224/0361 ,  H01L2224/03616 ,  H01L2224/0381 ,  H01L2224/05647 ,  H01L2224/05687 ,  H01L2224/08145 ,  H01L2224/74 ,  H01L2224/7501 ,  H01L2224/75101 ,  H01L2224/7565 ,  H01L2224/75753 ,  H01L2224/75824 ,  H01L2224/80004 ,  H01L2224/80007 ,  H01L2224/8001 ,  H01L2224/80011 ,  H01L2224/80013 ,  H01L2224/80014 ,  H01L2224/80065 ,  H01L2224/80075 ,  H01L2224/80097 ,  H01L2224/80121 ,  H01L2224/80136 ,  H01L2224/80203 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/83889 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/1461 ,  H01L2924/351 ,  Y10T156/15 ,  Y10T156/1744 ,  H01L2924/00012 ,  H01L2224/80 ,  H01L2924/05442 ,  H01L2924/00

Abstract: Hybrid bonding systems and methods for semiconductor wafers are disclosed. In one embodiment, a hybrid bonding system for semiconductor wafers includes a chamber and a plurality of sub-chambers disposed within the chamber. A robotics handler is disposed within the chamber that is adapted to move a plurality of semiconductor wafers within the chamber between the plurality of sub-chambers. The plurality of sub-chambers includes a first sub-chamber adapted to remove a protection layer from the plurality of semiconductor wafers, and a second sub-chamber adapted to activate top surfaces of the plurality of semiconductor wafers prior to hybrid bonding the plurality of semiconductor wafers together. The plurality of sub-chambers also includes a third sub-chamber adapted to align the plurality of semiconductor wafers and hybrid bond the plurality of semiconductor wafers together.

Abstract translation: 公开了用于半导体晶片的混合键合系统和方法。 在一个实施例中，用于半导体晶片的混合键合系统包括腔室和设置在腔室内的多个子腔室。 机器人处理器设置在腔室内，其适于移动多个子室内的室内的多个半导体晶片。 多个子室包括适于从多个半导体晶片去除保护层的第一子室，以及适于在混合结合多个半导体之前激活多个半导体晶片的顶表面的第二子室 晶圆在一起 多个子室还包括适于对准多个半导体晶片并将多个半导体晶片混合地结合在一起的第三子室。