公开(公告)号：US20150097022A1

公开(公告)日：2015-04-09

申请号：US14504701

申请日：2014-10-02

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENE ALT

Inventor： Lea DI CIOCCIO ,  Yann BEILLIARD

IPC: B23K20/00 ,  H05K3/46 ,  H01L21/18 ,  B23K20/24 ,  B23K31/02

CPC classification number: B23K20/002 ,  B23K20/24 ,  B23K31/02 ,  B23K2101/36 ,  H01L21/187 ,  H01L24/05 ,  H01L24/06 ,  H01L24/74 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05009 ,  H01L2224/05571 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/05693 ,  H01L2224/06505 ,  H01L2224/06517 ,  H01L2224/08145 ,  H01L2224/75754 ,  H01L2224/80035 ,  H01L2224/80097 ,  H01L2224/80136 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/80906 ,  H01L2224/80935 ,  H01L2224/80948 ,  H01L2224/80986 ,  H01L2224/95 ,  H01L2225/06513 ,  H05K3/4611 ,  H01L2924/00012 ,  H01L2924/05442 ,  H01L2924/00014 ,  H01L2224/80001

Abstract: Method of assembly of a first element (I) and a second element (II) each having an assembly surface, at least one of the assembly surfaces comprising recessed metal portions (6, 106) surrounded by dielectric materials (4, 104) comprising: A) a step to bring the two assembly surfaces into contact without application of pressure such that direct bonding is obtained between the assembly surfaces, said first and second assemblies (I, II) forming a stack with a given thickness (e), B) a heat treatment step of said stack during which the back faces (10, 110) of the first (I) and the second (II) elements are held in position so that they are held at a fixed distance (E) between the given stack thickness+/−2 nm.

Abstract translation: 第一元件（I）和第二元件（II）的组装方法，每个元件（I）和第二元件（II）均具有组件表面，所述组装表面中的至少一个包括由电介质材料（4,104）包围的凹入的金属部分（6,106），包括： A）在不施加压力的情况下使两个组装表面接触的步骤，使得在组装表面之间获得直接接合，所述第一和第二组件（I，II）形成具有给定厚度（e）的叠层，B） 所述堆叠的热处理步骤，其中第一（I）和第二（II）元件的背面（10,110）保持在适当位置，使得它们被保持在给定叠层之间的固定距离（E） 厚度+/- 2nm。

公开(公告)号：US20180254267A1

公开(公告)日：2018-09-06

申请号：US15971274

申请日：2018-05-04

Applicant: FUJI ELECTRIC CO., LTD.

Inventor： Kenichiro SATO

IPC: H01L25/18 ,  H01L21/67 ,  H01L23/495 ,  H01L25/07 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L25/18 ,  H01L21/67121 ,  H01L21/67259 ,  H01L23/3107 ,  H01L23/49541 ,  H01L23/49579 ,  H01L24/05 ,  H01L24/09 ,  H01L24/37 ,  H01L24/40 ,  H01L24/48 ,  H01L24/49 ,  H01L24/77 ,  H01L24/84 ,  H01L24/85 ,  H01L25/072 ,  H01L25/50 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/37011 ,  H01L2224/371 ,  H01L2224/37124 ,  H01L2224/37147 ,  H01L2224/37599 ,  H01L2224/40095 ,  H01L2224/40225 ,  H01L2224/40227 ,  H01L2224/45015 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/73221 ,  H01L2224/73271 ,  H01L2224/77272 ,  H01L2224/77702 ,  H01L2224/77705 ,  H01L2224/80121 ,  H01L2224/80136 ,  H01L2224/80815 ,  H01L2224/85121 ,  H01L2224/85136 ,  H01L2224/85801 ,  H01L2924/00014 ,  H01L2924/13055 ,  H01L2924/172 ,  H01L2924/17724 ,  H01L2924/17747 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00 ,  H01L2924/207

Abstract: A method of manufacturing a semiconductor device that includes an insulated circuit board having a conductive pattern, a first semiconductor chip with a rectangular shape connected through a first joining material to the conductive pattern, a second semiconductor chip with a rectangular shape disposed on the conductive pattern separated from the first semiconductor chip and connected through a second joining material to the conductive pattern, a terminal disposed above the semiconductor chips, respectively connected to the first and second semiconductor chips through third and fourth joining materials, the terminal having a through-hole above a place between the first and second semiconductor chips, the method including a positioning step in which the first and second semiconductor chips are respectively positioned at at least three positioning places, and at least one of the positioning places is positioned with a positioning member inserted into the through-hole.

公开(公告)号：US09048283B2

公开(公告)日：2015-06-02

申请号：US13542507

申请日：2012-07-05

Applicant: Ping-Yin Liu ,  Shih-Wei Lin ,  Xin-Hua Huang ,  Lan-Lin Chao ,  Chia-Shiung Tsai

Inventor： Ping-Yin Liu ,  Shih-Wei Lin ,  Xin-Hua Huang ,  Lan-Lin Chao ,  Chia-Shiung Tsai

IPC: H01L21/30 ,  H01L23/00

CPC classification number: H01L24/80 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/27 ,  H01L24/74 ,  H01L24/94 ,  H01L2224/02215 ,  H01L2224/0361 ,  H01L2224/03616 ,  H01L2224/0381 ,  H01L2224/05647 ,  H01L2224/05687 ,  H01L2224/08145 ,  H01L2224/74 ,  H01L2224/7501 ,  H01L2224/75101 ,  H01L2224/7565 ,  H01L2224/75753 ,  H01L2224/75824 ,  H01L2224/80004 ,  H01L2224/80007 ,  H01L2224/8001 ,  H01L2224/80011 ,  H01L2224/80013 ,  H01L2224/80014 ,  H01L2224/80065 ,  H01L2224/80075 ,  H01L2224/80097 ,  H01L2224/80121 ,  H01L2224/80136 ,  H01L2224/80203 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/83889 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/1461 ,  H01L2924/351 ,  Y10T156/15 ,  Y10T156/1744 ,  H01L2924/00012 ,  H01L2224/80 ,  H01L2924/05442 ,  H01L2924/00

Abstract: Hybrid bonding systems and methods for semiconductor wafers are disclosed. In one embodiment, a hybrid bonding system for semiconductor wafers includes a chamber and a plurality of sub-chambers disposed within the chamber. A robotics handler is disposed within the chamber that is adapted to move a plurality of semiconductor wafers within the chamber between the plurality of sub-chambers. The plurality of sub-chambers includes a first sub-chamber adapted to remove a protection layer from the plurality of semiconductor wafers, and a second sub-chamber adapted to activate top surfaces of the plurality of semiconductor wafers prior to hybrid bonding the plurality of semiconductor wafers together. The plurality of sub-chambers also includes a third sub-chamber adapted to align the plurality of semiconductor wafers and hybrid bond the plurality of semiconductor wafers together.

Abstract translation: 公开了用于半导体晶片的混合键合系统和方法。 在一个实施例中，用于半导体晶片的混合键合系统包括腔室和设置在腔室内的多个子腔室。 机器人处理器设置在腔室内，其适于移动多个子室内的室内的多个半导体晶片。 多个子室包括适于从多个半导体晶片去除保护层的第一子室，以及适于在混合结合多个半导体之前激活多个半导体晶片的顶表面的第二子室 晶圆在一起 多个子室还包括适于对准多个半导体晶片并将多个半导体晶片混合地结合在一起的第三子室。

公开(公告)号：US20170352641A1

公开(公告)日：2017-12-07

申请号：US15173816

申请日：2016-06-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien-Ling HWANG ,  Hsin-Hung LIAO ,  Yu-Ting CHIU ,  Ching-Hua HSIEH

IPC: H01L23/00

CPC classification number: H01L24/81 ,  H01L24/09 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/742 ,  H01L24/75 ,  H01L24/83 ,  H01L2224/11003 ,  H01L2224/11005 ,  H01L2224/11334 ,  H01L2224/13017 ,  H01L2224/751 ,  H01L2224/75753 ,  H01L2224/80127 ,  H01L2224/80136 ,  H01L2224/81024 ,  H01L2224/81201 ,  H01L2224/81345 ,  H01L2924/00012

Abstract: A method for mounting components on a substrate is provided. The method includes providing a positioning plate which has a plurality of through holes. The method further includes supplying components each having a longitudinal portion on the positioning plate. The method also includes performing a component alignment process to put the longitudinal portions of the components in the through holes. In addition, the method includes connecting a substrate to the components which have their longitudinal portions in the through holes and removing the positioning plate.

公开(公告)号：US20140011324A1

公开(公告)日：2014-01-09

申请号：US13542507

申请日：2012-07-05

Applicant: Ping-Yin Liu ,  Shih-Wei Lin ,  Xin-Hua Huang ,  Lan-Lin Chao ,  Chia-Shiung Tsai

Inventor： Ping-Yin Liu ,  Shih-Wei Lin ,  Xin-Hua Huang ,  Lan-Lin Chao ,  Chia-Shiung Tsai

IPC: H01L21/50

CPC classification number: H01L24/80 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/27 ,  H01L24/74 ,  H01L24/94 ,  H01L2224/02215 ,  H01L2224/0361 ,  H01L2224/03616 ,  H01L2224/0381 ,  H01L2224/05647 ,  H01L2224/05687 ,  H01L2224/08145 ,  H01L2224/74 ,  H01L2224/7501 ,  H01L2224/75101 ,  H01L2224/7565 ,  H01L2224/75753 ,  H01L2224/75824 ,  H01L2224/80004 ,  H01L2224/80007 ,  H01L2224/8001 ,  H01L2224/80011 ,  H01L2224/80013 ,  H01L2224/80014 ,  H01L2224/80065 ,  H01L2224/80075 ,  H01L2224/80097 ,  H01L2224/80121 ,  H01L2224/80136 ,  H01L2224/80203 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/83889 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/1461 ,  H01L2924/351 ,  Y10T156/15 ,  Y10T156/1744 ,  H01L2924/00012 ,  H01L2224/80 ,  H01L2924/05442 ,  H01L2924/00

Abstract: Hybrid bonding systems and methods for semiconductor wafers are disclosed. In one embodiment, a hybrid bonding system for semiconductor wafers includes a chamber and a plurality of sub-chambers disposed within the chamber. A robotics handler is disposed within the chamber that is adapted to move a plurality of semiconductor wafers within the chamber between the plurality of sub-chambers. The plurality of sub-chambers includes a first sub-chamber adapted to remove a protection layer from the plurality of semiconductor wafers, and a second sub-chamber adapted to activate top surfaces of the plurality of semiconductor wafers prior to hybrid bonding the plurality of semiconductor wafers together. The plurality of sub-chambers also includes a third sub-chamber adapted to align the plurality of semiconductor wafers and hybrid bond the plurality of semiconductor wafers together.

Abstract translation: 公开了用于半导体晶片的混合键合系统和方法。 在一个实施例中，用于半导体晶片的混合键合系统包括腔室和设置在腔室内的多个子腔室。 机器人处理器设置在腔室内，其适于移动多个子室内的室内的多个半导体晶片。 多个子室包括适于从多个半导体晶片去除保护层的第一子室，以及适于在混合结合多个半导体之前激活多个半导体晶片的顶表面的第二子室 晶圆在一起 多个子室还包括适于对准多个半导体晶片并将多个半导体晶片混合地结合在一起的第三子室。

公开(公告)号：US12040208B2

公开(公告)日：2024-07-16

申请号：US17540859

申请日：2021-12-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Myunghee Kim ,  Seungran Park ,  Youngki Jung ,  Chulgyu Jung

IPC: H01L21/68 ,  H01L23/00 ,  H01L25/16

CPC classification number: H01L21/68 ,  H01L24/95 ,  H01L25/167 ,  H01L24/80 ,  H01L24/83 ,  H01L2224/80085 ,  H01L2224/80136 ,  H01L2224/80203 ,  H01L2224/80805 ,  H01L2224/83085 ,  H01L2224/83136 ,  H01L2224/83201 ,  H01L2224/95085 ,  H01L2224/95101 ,  H01L2224/95136 ,  H01L2924/12041

Abstract: A guide apparatus configured to transfer light-emitting devices in a liquid onto a substrate is provided. The guide apparatus includes a base configured to support the substrate; and a guide member configured to couple with the base to be seated on a mounting surface of the substrate in a state in which the substrate is supported on a surface of the base, wherein the guide member includes guide holes configured to respectively guide the light-emitting devices in the liquid to be disposed on the mounting surface of the substrate.

公开(公告)号：US09991242B2

公开(公告)日：2018-06-05

申请号：US14620184

申请日：2015-02-11

Applicant: FUJI ELECTRIC CO., LTD.

Inventor： Kenichiro Sato

IPC: H01L23/00 ,  H01L25/18 ,  H01L21/67 ,  H01L23/495 ,  H01L25/00 ,  H01L25/07

CPC classification number: H01L25/18 ,  H01L21/67121 ,  H01L21/67259 ,  H01L23/49541 ,  H01L23/49579 ,  H01L24/05 ,  H01L24/09 ,  H01L24/37 ,  H01L24/40 ,  H01L24/48 ,  H01L24/49 ,  H01L24/77 ,  H01L24/84 ,  H01L24/85 ,  H01L25/072 ,  H01L25/50 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/37011 ,  H01L2224/371 ,  H01L2224/37124 ,  H01L2224/37147 ,  H01L2224/37599 ,  H01L2224/40095 ,  H01L2224/40225 ,  H01L2224/40227 ,  H01L2224/45015 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/73221 ,  H01L2224/73271 ,  H01L2224/77272 ,  H01L2224/77702 ,  H01L2224/77705 ,  H01L2224/80121 ,  H01L2224/80136 ,  H01L2224/80815 ,  H01L2224/85121 ,  H01L2224/85136 ,  H01L2224/85801 ,  H01L2924/00014 ,  H01L2924/13055 ,  H01L2924/172 ,  H01L2924/17724 ,  H01L2924/17747 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00 ,  H01L2924/207

Abstract: A semiconductor device has a plurality of small-sized semiconductor chips disposed between an insulated circuit board having a conductive pattern and a terminal. The semiconductor device exhibits a high accuracy in positioning the semiconductor chips. The semiconductor device includes an insulated circuit board having a conductive pattern, a first semiconductor chip with a rectangular shape connected to the conductive pattern through a first joining material, a second semiconductor chip with a rectangular shape, disposed on the conductive pattern separated from the first semiconductor chip and connected to the conductive pattern through a second joining material, and a terminal disposed above the first semiconductor chip and the second semiconductor chip, connected to the first semiconductor chip through a third joining material, and connected to the second semiconductor chip through a fourth joining material. The terminal has a through-hole above a place between the first semiconductor chip and the second semiconductor chip.

公开(公告)号：US20150287694A1

公开(公告)日：2015-10-08

申请号：US14725266

申请日：2015-05-29

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ping-Yin Liu ,  Shih-Wei Lin ,  Xin-Hua Huang ,  Lan-Lin Chao ,  Chia-Shiung Tsai

IPC: H01L23/00

CPC classification number: H01L24/80 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/27 ,  H01L24/74 ,  H01L24/94 ,  H01L2224/02215 ,  H01L2224/0361 ,  H01L2224/03616 ,  H01L2224/0381 ,  H01L2224/05647 ,  H01L2224/05687 ,  H01L2224/08145 ,  H01L2224/74 ,  H01L2224/7501 ,  H01L2224/75101 ,  H01L2224/7565 ,  H01L2224/75753 ,  H01L2224/75824 ,  H01L2224/80004 ,  H01L2224/80007 ,  H01L2224/8001 ,  H01L2224/80011 ,  H01L2224/80013 ,  H01L2224/80014 ,  H01L2224/80065 ,  H01L2224/80075 ,  H01L2224/80097 ,  H01L2224/80121 ,  H01L2224/80136 ,  H01L2224/80203 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/83889 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/1461 ,  H01L2924/351 ,  Y10T156/15 ,  Y10T156/1744 ,  H01L2924/00012 ,  H01L2224/80 ,  H01L2924/05442 ,  H01L2924/00

Abstract: Hybrid bonding systems and methods for semiconductor wafers are disclosed. In one embodiment, a hybrid bonding system for semiconductor wafers includes a chamber and a plurality of sub-chambers disposed within the chamber. A robotics handler is disposed within the chamber that is adapted to move a plurality of semiconductor wafers within the chamber between the plurality of sub-chambers. The plurality of sub-chambers includes a first sub-chamber adapted to remove a protection layer from the plurality of semiconductor wafers, and a second sub-chamber adapted to activate top surfaces of the plurality of semiconductor wafers prior to hybrid bonding the plurality of semiconductor wafers together. The plurality of sub-chambers also includes a third sub-chamber adapted to align the plurality of semiconductor wafers and hybrid bond the plurality of semiconductor wafers together.

Abstract translation: 公开了用于半导体晶片的混合键合系统和方法。 在一个实施例中，用于半导体晶片的混合键合系统包括腔室和设置在腔室内的多个子腔室。 机器人处理器设置在腔室内，其适于移动多个子室内的室内的多个半导体晶片。 多个子室包括适于从多个半导体晶片去除保护层的第一子室，以及适于在混合结合多个半导体之前激活多个半导体晶片的顶表面的第二子室 晶圆在一起 多个子室还包括适于对准多个半导体晶片并将多个半导体晶片混合地结合在一起的第三子室。

公开(公告)号：US20190051628A1

公开(公告)日：2019-02-14

申请号：US16160572

申请日：2018-10-15

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ping-Yin Liu ,  Shih-Wei Lin ,  Xin-Hua Huang ,  Lan-Lin Chao ,  Chia-Shiung Tsai

IPC: H01L23/00

CPC classification number: H01L24/80 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/27 ,  H01L24/74 ,  H01L24/94 ,  H01L2224/02215 ,  H01L2224/0361 ,  H01L2224/03616 ,  H01L2224/0381 ,  H01L2224/05647 ,  H01L2224/05687 ,  H01L2224/08145 ,  H01L2224/74 ,  H01L2224/7501 ,  H01L2224/75101 ,  H01L2224/7565 ,  H01L2224/75753 ,  H01L2224/75824 ,  H01L2224/80 ,  H01L2224/80004 ,  H01L2224/80007 ,  H01L2224/8001 ,  H01L2224/80011 ,  H01L2224/80013 ,  H01L2224/80014 ,  H01L2224/80065 ,  H01L2224/80075 ,  H01L2224/80097 ,  H01L2224/80121 ,  H01L2224/80136 ,  H01L2224/80203 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/83889 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/1461 ,  H01L2924/351 ,  Y10T156/15 ,  Y10T156/1744 ,  H01L2924/00012 ,  H01L2924/05442 ,  H01L2924/00

Abstract: Hybrid bonding systems and methods for semiconductor wafers are disclosed. In one embodiment, a hybrid bonding system for semiconductor wafers includes a chamber and a plurality of sub-chambers disposed within the chamber. A robotics handler is disposed within the chamber that is adapted to move a plurality of semiconductor wafers within the chamber between the plurality of sub-chambers. The plurality of sub-chambers includes a first sub-chamber adapted to remove a protection layer from the plurality of semiconductor wafers, and a second sub-chamber adapted to activate top surfaces of the plurality of semiconductor wafers prior to hybrid bonding the plurality of semiconductor wafers together. The plurality of sub-chambers also includes a third sub-chamber adapted to align the plurality of semiconductor wafers and hybrid bond the plurality of semiconductor wafers together.

公开(公告)号：US20170358551A1

公开(公告)日：2017-12-14

申请号：US15689982

申请日：2017-08-29

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ping-Yin Liu ,  Shih-Wei Lin ,  Xin-Hua Huang ,  Lan-Lin Chao ,  Chia-Shiung Tsai

IPC: H01L23/00

CPC classification number: H01L24/80 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/27 ,  H01L24/74 ,  H01L24/94 ,  H01L2224/02215 ,  H01L2224/0361 ,  H01L2224/03616 ,  H01L2224/0381 ,  H01L2224/05647 ,  H01L2224/05687 ,  H01L2224/08145 ,  H01L2224/74 ,  H01L2224/7501 ,  H01L2224/75101 ,  H01L2224/7565 ,  H01L2224/75753 ,  H01L2224/75824 ,  H01L2224/80004 ,  H01L2224/80007 ,  H01L2224/8001 ,  H01L2224/80011 ,  H01L2224/80013 ,  H01L2224/80014 ,  H01L2224/80065 ,  H01L2224/80075 ,  H01L2224/80097 ,  H01L2224/80121 ,  H01L2224/80136 ,  H01L2224/80203 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/83889 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/1461 ,  H01L2924/351 ,  Y10T156/15 ,  Y10T156/1744 ,  H01L2924/00012 ,  H01L2224/80 ,  H01L2924/05442 ,  H01L2924/00

Abstract: Hybrid bonding systems and methods for semiconductor wafers are disclosed. In one embodiment, a hybrid bonding system for semiconductor wafers includes a chamber and a plurality of sub-chambers disposed within the chamber. A robotics handler is disposed within the chamber that is adapted to move a plurality of semiconductor wafers within the chamber between the plurality of sub-chambers. The plurality of sub-chambers includes a first sub-chamber adapted to remove a protection layer from the plurality of semiconductor wafers, and a second sub-chamber adapted to activate top surfaces of the plurality of semiconductor wafers prior to hybrid bonding the plurality of semiconductor wafers together. The plurality of sub-chambers also includes a third sub-chamber adapted to align the plurality of semiconductor wafers and hybrid bond the plurality of semiconductor wafers together.