公开(公告)号：US20240243085A1

公开(公告)日：2024-07-18

申请号：US18517681

申请日：2023-11-22

Applicant: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.

Inventor： Paul M. Enquist

IPC: H01L23/00 ,  H01L21/50 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L24/09 ,  H01L21/50 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/80 ,  H01L24/89 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/036 ,  H01L2224/03616 ,  H01L2224/03825 ,  H01L2224/05005 ,  H01L2224/05007 ,  H01L2224/05026 ,  H01L2224/05078 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/0556 ,  H01L2224/05561 ,  H01L2224/05562 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/05666 ,  H01L2224/05676 ,  H01L2224/05681 ,  H01L2224/05684 ,  H01L2224/05686 ,  H01L2224/08112 ,  H01L2224/08121 ,  H01L2224/08123 ,  H01L2224/08145 ,  H01L2224/08147 ,  H01L2224/80011 ,  H01L2224/80031 ,  H01L2224/80035 ,  H01L2224/80047 ,  H01L2224/80075 ,  H01L2224/80097 ,  H01L2224/80099 ,  H01L2224/8019 ,  H01L2224/80194 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/80935 ,  H01L2224/80986 ,  H01L2225/06513

Abstract: A method for forming a direct hybrid bond and a device resulting from a direct hybrid bond including a first substrate having a first set of metallic bonding pads, preferably connected to a device or circuit, capped by a conductive barrier, and having a first non-metallic region adjacent to the metallic bonding pads on the first substrate, a second substrate having a second set of metallic bonding pads capped by a second conductive barrier, aligned with the first set of metallic bonding pads, preferably connected to a device or circuit, and having a second non-metallic region adjacent to the metallic bonding pads on the second substrate, and a contact-bonded interface between the first and second set of metallic bonding pads capped by conductive barriers formed by contact bonding of the first non-metallic region to the second non-metallic region.

公开(公告)号：US11830838B2

公开(公告)日：2023-11-28

申请号：US17677161

申请日：2022-02-22

Applicant: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.

Inventor： Paul M. Enquist

IPC: H01L23/00 ,  H01L21/50 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L24/09 ,  H01L21/50 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/80 ,  H01L24/89 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/036 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03616 ,  H01L2224/03825 ,  H01L2224/05005 ,  H01L2224/05007 ,  H01L2224/05026 ,  H01L2224/0556 ,  H01L2224/0557 ,  H01L2224/05078 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05562 ,  H01L2224/05573 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/05666 ,  H01L2224/05676 ,  H01L2224/05681 ,  H01L2224/05684 ,  H01L2224/05686 ,  H01L2224/08112 ,  H01L2224/08121 ,  H01L2224/08123 ,  H01L2224/08145 ,  H01L2224/08147 ,  H01L2224/80011 ,  H01L2224/8019 ,  H01L2224/80031 ,  H01L2224/80035 ,  H01L2224/80047 ,  H01L2224/80075 ,  H01L2224/80097 ,  H01L2224/80099 ,  H01L2224/80194 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/80935 ,  H01L2224/80986 ,  H01L2225/06513 ,  H01L2224/03462 ,  H01L2924/00014 ,  H01L2224/0345 ,  H01L2924/00014 ,  H01L2224/03452 ,  H01L2924/00014 ,  H01L2224/29339 ,  H01L2924/00014 ,  H01L2224/29386 ,  H01L2224/80895 ,  H01L2924/053 ,  H01L2224/80986 ,  H01L2224/80896 ,  H01L2224/05124 ,  H01L2924/00014 ,  H01L2224/05147 ,  H01L2924/00014 ,  H01L2224/05686 ,  H01L2924/04941 ,  H01L2224/05686 ,  H01L2924/04953 ,  H01L2224/05684 ,  H01L2924/049 ,  H01L2224/05676 ,  H01L2924/053 ,  H01L2224/05681 ,  H01L2924/01014 ,  H01L2924/049 ,  H01L2224/05666 ,  H01L2924/01014 ,  H01L2924/049 ,  H01L2224/05684 ,  H01L2924/01005 ,  H01L2924/049 ,  H01L2224/05655 ,  H01L2924/051 ,  H01L2924/00014 ,  H01L2224/05657 ,  H01L2924/01074 ,  H01L2224/05657 ,  H01L2924/01074 ,  H01L2924/042

Abstract: A method for forming a direct hybrid bond and a device resulting from a direct hybrid bond including a first substrate having a first set of metallic bonding pads, preferably connected to a device or circuit, capped by a conductive barrier, and having a first non-metallic region adjacent to the metallic bonding pads on the first substrate, a second substrate having a second set of metallic bonding pads capped by a second conductive barrier, aligned with the first set of metallic bonding pads, preferably connected to a device or circuit, and having a second non-metallic region adjacent to the metallic bonding pads on the second substrate, and a contact-bonded interface between the first and second set of metallic bonding pads capped by conductive barriers formed by contact bonding of the first non-metallic region to the second non-metallic region.

公开(公告)号：US20240088196A1

公开(公告)日：2024-03-14

申请号：US18513410

申请日：2023-11-17

Applicant: CANON KABUSHIKI KAISHA

Inventor： Nobuyuki Endo ,  Tetsuya Itano ,  Kazuo Yamazaki ,  Kyouhei Watanabe ,  Junji Iwata

IPC: H01L27/146 ,  H01L31/04

CPC classification number: H01L27/1469 ,  H01L27/14634 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/14687 ,  H01L27/14689 ,  H01L31/04 ,  H01L2224/05655 ,  H01L2224/80035 ,  H01L2224/80895 ,  H01L2224/80935

Abstract: A member for a solid-state image pickup device having a bonding plane with no gaps and a method for manufacturing the same are provided. The manufacturing method includes the steps of providing a first substrate provided with a photoelectric converter on its primary face and a first wiring structure, providing a second substrate provided with a part of a peripheral circuit on its primary face and a second wiring structure, and performing bonding so that the first substrate, the first wiring structure, the second wiring structure, and the second substrate are disposed in this order. In addition, at least one of an upper face of the first wiring structure and an upper face of the second wiring structure has a concave portion, and a conductive material forms a bottom face of the concave portion.

公开(公告)号：US20180277585A1

公开(公告)日：2018-09-27

申请号：US15992908

申请日：2018-05-30

Applicant: Sony Corporation

Inventor： Yoshihisa Kagawa ,  Kenichi Aoyagi ,  Yoshiya Hagimoto ,  Nobutoshi Fujii

IPC: H01L27/146 ,  H01L21/768 ,  H04N5/369 ,  H01L23/528 ,  H01L23/532 ,  H01L23/00 ,  H01L27/06 ,  H01L23/48

CPC classification number: H01L27/14636 ,  H01L21/76807 ,  H01L21/7684 ,  H01L21/76841 ,  H01L21/76843 ,  H01L23/481 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53295 ,  H01L23/564 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/80 ,  H01L24/83 ,  H01L27/0688 ,  H01L27/14609 ,  H01L27/14621 ,  H01L27/14625 ,  H01L27/1464 ,  H01L27/14645 ,  H01L27/1469 ,  H01L2221/1031 ,  H01L2224/02245 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05546 ,  H01L2224/05547 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05578 ,  H01L2224/05647 ,  H01L2224/05686 ,  H01L2224/08121 ,  H01L2224/08145 ,  H01L2224/0903 ,  H01L2224/80011 ,  H01L2224/80013 ,  H01L2224/80035 ,  H01L2224/80091 ,  H01L2224/80097 ,  H01L2224/80203 ,  H01L2224/80345 ,  H01L2224/80357 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/80935 ,  H01L2224/83345 ,  H01L2924/00014 ,  H01L2924/053 ,  H01L2924/12043 ,  H01L2924/13091 ,  H04N5/369 ,  H01L2924/00012 ,  H01L2924/05442 ,  H01L2924/05042 ,  H01L2924/049 ,  H01L2924/00 ,  H01L2224/05552

Abstract: Disclosed herein is a semiconductor device, including: a first substrate including a first electrode, and a first insulating film configured from a diffusion preventing material for the first electrode and covering a periphery of the first electrode, the first electrode and the first insulating film cooperating with each other to configure a bonding face; and a second substrate bonded to and provided on the first substrate and including a second electrode joined to the first electrode, and a second insulating film configured from a diffusion preventing material for the second electrode and covering a periphery of the second electrode, the second electrode and the second insulating film cooperating with each other to configure a bonding face to the first substrate.

公开(公告)号：US20230268308A1

公开(公告)日：2023-08-24

申请号：US18067617

申请日：2022-12-16

Applicant: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.

Inventor： Gaius Gillman Fountain, JR. ,  Chandrasekhar Mandalapu ,  Cyprian Emeka Uzoh ,  Jeremy Alfred Theil

IPC: H01L23/00

CPC classification number: H01L24/27 ,  H01L24/30 ,  H01L24/32 ,  H01L24/83 ,  H01L24/29 ,  H01L24/05 ,  H01L24/06 ,  H01L24/03 ,  H01L2224/83905 ,  H01L2224/27462 ,  H01L2224/27616 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/29186 ,  H01L2224/30505 ,  H01L2224/3003 ,  H01L2224/30131 ,  H01L2224/3015 ,  H01L2224/30517 ,  H01L2224/32145 ,  H01L2224/83895 ,  H01L2224/83896 ,  H01L2224/80986 ,  H01L2224/80035 ,  H01L2224/80935 ,  H01L2224/05547 ,  H01L2224/05181 ,  H01L2224/06155 ,  H01L2224/06152 ,  H01L2224/80357 ,  H01L2224/80896 ,  H01L2224/08145 ,  H01L2224/0603 ,  H01L24/80 ,  H01L2224/03616 ,  H01L2224/05166 ,  H01L2224/06131 ,  H01L2224/80895 ,  H01L2224/03462 ,  H01L2224/80948 ,  H01L2224/05647 ,  H01L2224/06136 ,  H01L2224/05155

Abstract: Representative implementations of techniques and methods include chemical mechanical polishing for hybrid bonding. The disclosed methods include depositing and patterning a dielectric layer on a substrate to form openings in the dielectric layer, depositing a barrier layer over the dielectric layer and within a first portion of the openings, and depositing a conductive structure over the barrier layer and within a second portion of the openings not occupied by the barrier layer, at least a portion of the conductive structure in the second portion of the openings coupled or contacting electrical circuitry within the substrate. Additionally, the conductive structure is polished to reveal portions of the barrier layer deposited over the dielectric layer and not in the second portion of the openings. Further, the barrier layer is polished with a selective polish to reveal a bonding surface on or at the dielectric layer.

公开(公告)号：US20180233479A1

公开(公告)日：2018-08-16

申请号：US15434606

申请日：2017-02-16

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： PO-CHUN LIN ,  CHIN-LUNG CHU

IPC: H01L23/00 ,  H01L21/306 ,  H01L21/324 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L24/83 ,  H01L21/30625 ,  H01L21/324 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53228 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/80 ,  H01L2224/0347 ,  H01L2224/0361 ,  H01L2224/03612 ,  H01L2224/03614 ,  H01L2224/0384 ,  H01L2224/039 ,  H01L2224/05557 ,  H01L2224/05571 ,  H01L2224/05578 ,  H01L2224/05647 ,  H01L2224/05687 ,  H01L2224/08145 ,  H01L2224/08147 ,  H01L2224/80035 ,  H01L2224/80357 ,  H01L2224/80801 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/80935 ,  H01L2224/80986 ,  H01L2924/00014 ,  H01L2924/05442 ,  H01L2224/034

Abstract: The present disclosure is directed to a semiconductor apparatus having a plurality of bonded semiconductor devices formed by a fusion bonding technique and a method for preparing the same. The semiconductor devices have conductive portions with higher coefficient of thermal expansion than their dielectric portions. By forming the depression to provide a space for the volume expansion of the conductive portion with higher coefficient of thermal expansion during the subsequent thermal treating process of the fusion bonding, the semiconductor apparatus formed of semiconductor devices by the fusion bonding technique does not exhibit a lateral protrusion into the interface between the two dielectric portions. As a result, the failure of the electrical function due to the lateral protrusion is effectively eliminated.

公开(公告)号：US10038024B2

公开(公告)日：2018-07-31

申请号：US15228860

申请日：2016-08-04

Applicant: Sony Corporation

Inventor： Yoshihisa Kagawa ,  Kenichi Aoyagi ,  Yoshiya Hagimoto ,  Nobutoshi Fujii

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L27/146 ,  H01L21/768 ,  H01L23/00 ,  H04N5/369 ,  H01L23/528 ,  H01L23/532 ,  H01L27/06

CPC classification number: H01L27/14636 ,  H01L21/76807 ,  H01L21/7684 ,  H01L21/76841 ,  H01L21/76843 ,  H01L23/481 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53295 ,  H01L23/564 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/80 ,  H01L24/83 ,  H01L27/0688 ,  H01L27/14609 ,  H01L27/14621 ,  H01L27/14625 ,  H01L27/1464 ,  H01L27/14645 ,  H01L27/1469 ,  H01L2221/1031 ,  H01L2224/02245 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05546 ,  H01L2224/05547 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05578 ,  H01L2224/05647 ,  H01L2224/05686 ,  H01L2224/08121 ,  H01L2224/08145 ,  H01L2224/0903 ,  H01L2224/80011 ,  H01L2224/80013 ,  H01L2224/80035 ,  H01L2224/80091 ,  H01L2224/80097 ,  H01L2224/80203 ,  H01L2224/80345 ,  H01L2224/80357 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/80935 ,  H01L2224/83345 ,  H01L2924/00014 ,  H01L2924/053 ,  H01L2924/12043 ,  H01L2924/13091 ,  H04N5/369 ,  H01L2924/00012 ,  H01L2924/05442 ,  H01L2924/05042 ,  H01L2924/049 ,  H01L2924/00 ,  H01L2224/05552

Abstract: Disclosed herein is a semiconductor device, including: a first substrate including a first electrode, and a first insulating film configured from a diffusion preventing material for the first electrode and covering a periphery of the first electrode, the first electrode and the first insulating film cooperating with each other to configure a bonding face; and a second substrate bonded to and provided on the first substrate and including a second electrode joined to the first electrode, and a second insulating film configured from a diffusion preventing material for the second electrode and covering a periphery of the second electrode, the second electrode and the second insulating film cooperating with each other to configure a bonding face to the first substrate.

公开(公告)号：US11843023B2

公开(公告)日：2023-12-12

申请号：US18056023

申请日：2022-11-16

Applicant: CANON KABUSHIKI KAISHA

Inventor： Nobuyuki Endo ,  Tetsuya Itano ,  Kazuo Yamazaki ,  Kyouhei Watanabe ,  Junji Iwata

IPC: H01L27/14 ,  H01L27/146 ,  H01L31/04

CPC classification number: H01L27/1469 ,  H01L27/1464 ,  H01L27/14634 ,  H01L27/14636 ,  H01L27/14687 ,  H01L27/14689 ,  H01L31/04 ,  H01L2224/05655 ,  H01L2224/80035 ,  H01L2224/80895 ,  H01L2224/80935

Abstract: A member for a solid-state image pickup device having a bonding plane with no gaps and a method for manufacturing the same are provided. The manufacturing method includes the steps of providing a first substrate provided with a photoelectric converter on its primary face and a first wiring structure, providing a second substrate provided with a part of a peripheral circuit on its primary face and a second wiring structure, and performing bonding so that the first substrate, the first wiring structure, the second wiring structure, and the second substrate are disposed in this order. In addition, at least one of an upper face of the first wiring structure and an upper face of the second wiring structure has a concave portion, and a conductive material forms a bottom face of the concave portion.

公开(公告)号：US20230223377A1

公开(公告)日：2023-07-13

申请号：US17805166

申请日：2022-06-02

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor： CHIH-WEI CHANG

IPC: H01L23/00

CPC classification number: H01L24/80 ,  H01L24/74 ,  H01L2224/80894 ,  H01L2224/80908 ,  H01L2224/80035 ,  H01L2224/8013

Abstract: A wafer bonding device includes: a first fixing apparatus fixing a first wafer, on which a first alignment mark is disposed; a second fixing apparatus fixing a second wafer, on which a second alignment mark is disposed, the second fixing apparatus being disposed opposite to the first fixing apparatus; a reflection member between the first and second fixing apparatuses; a mark reader which reads position information about the first and second alignment marks by means of the reflection member, for aligning the first wafer with the second wafer; and a heating apparatus, configured to heat the first wafer or the second wafer to thermally expand the first wafer or the second wafer so that the first alignment mark or the second alignment mark is located at a central position of a field of view of the mark reader. A wafer bonding method also is involved.

公开(公告)号：US20190244899A1

公开(公告)日：2019-08-08

申请号：US16388692

申请日：2019-04-18

Applicant: Invensas Bonding Technologies, Inc.

Inventor： Paul M. Enquist ,  Gaius Gillman Fountain, JR. ,  Javier A. DeLaCruz

IPC: H01L23/528 ,  H01L23/522 ,  H01L25/065 ,  H01L23/00 ,  H01L25/00 ,  H01L21/768

CPC classification number: H01L23/5283 ,  H01L21/76838 ,  H01L23/5226 ,  H01L24/02 ,  H01L24/05 ,  H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05541 ,  H01L2224/05551 ,  H01L2224/05552 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05578 ,  H01L2224/056 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05684 ,  H01L2224/0807 ,  H01L2224/08111 ,  H01L2224/08121 ,  H01L2224/08146 ,  H01L2224/08147 ,  H01L2224/08148 ,  H01L2224/08237 ,  H01L2224/08238 ,  H01L2224/16145 ,  H01L2224/80 ,  H01L2224/80035 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/80935 ,  H01L2225/06513 ,  H01L2225/06555 ,  H01L2225/06593 ,  H01L2924/013 ,  H01L2924/00014 ,  H01L2924/206 ,  H01L2924/00012

Abstract: A bonded device structure including a first substrate having a first set of conductive contact structures, preferably connected to a device or circuit, and having a first non-metallic region adjacent to the contact structures on the first substrate, a second substrate having a second set of conductive contact structures, preferably connected to a device or circuit, and having a second non-metallic region adjacent to the contact structures on the second substrate, and a contact-bonded interface between the first and second set of contact structures formed by contact bonding of the first non-metallic region to the second non-metallic region. The contact structures include elongated contact features, such as individual lines or lines connected in a grid, that are non-parallel on the two substrates, making contact at intersections. Alignment tolerances are thus improved while minimizing dishing and parasitic capacitance.