公开(公告)号：US20180076160A1

公开(公告)日：2018-03-15

申请号：US15813311

申请日：2017-11-15

Applicant: International Business Machines Corporation

Inventor： Brian M. Erwin ,  Brittany L. Hedrick ,  Nicholas A. Polomoff ,  TaeHo Kim ,  Matthew E. Souter

IPC: H01L23/00

CPC classification number: H01L24/11 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/03632 ,  H01L2224/0381 ,  H01L2224/0382 ,  H01L2224/04105 ,  H01L2224/05647 ,  H01L2224/11009 ,  H01L2224/11632 ,  H01L2224/1181 ,  H01L2224/1182 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13686 ,  H01L2924/05042 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/01029 ,  H01L2924/053

Abstract: A semiconductor structure includes an electrically conductive structure formed upon an uppermost organic layer of a semiconductor substrate. A capping layer is formed upon the uppermost organic layer covering the electrically conductive structure. A maskless selective removal lasering technique ejects portions of the capping layer while retaining the portion of the capping layer covering the electrically conductive structure. Portions of the capping layer are ejected from the uppermost organic layer by a shockwave as a result of the laser beam vaporizing the uppermost organic layer of the semiconductor substrate. Portions of the capping layer contacting the electrically conductive structure are retained by the conductive structure dissipating heat from the laser that would otherwise vaporize the uppermost organic layer of the semiconductor substrate.

公开(公告)号：US20170352633A1

公开(公告)日：2017-12-07

申请号：US15684054

申请日：2017-08-23

Applicant: Micron Technology, Inc.

Inventor： Giorgio Mariottini ,  Sameer Vadhavkar ,  Wayne Huang ,  Anilkumar Chandolu ,  Mark Bossler

IPC: H01L23/00

CPC classification number: H01L24/05 ,  H01L21/481 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02135 ,  H01L2224/02166 ,  H01L2224/0219 ,  H01L2224/03013 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/03472 ,  H01L2224/0348 ,  H01L2224/0361 ,  H01L2224/03906 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05007 ,  H01L2224/05009 ,  H01L2224/0508 ,  H01L2224/05082 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05547 ,  H01L2224/05553 ,  H01L2224/05555 ,  H01L2224/05565 ,  H01L2224/05566 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05686 ,  H01L2224/05687 ,  H01L2224/0569 ,  H01L2224/10126 ,  H01L2224/10145 ,  H01L2224/1146 ,  H01L2224/11472 ,  H01L2224/11906 ,  H01L2224/13018 ,  H01L2224/13023 ,  H01L2224/13026 ,  H01L2224/13083 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/94 ,  H01L2924/014 ,  H01L2924/07025 ,  H01L2924/3651 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/00014 ,  H01L2224/05655 ,  H01L2924/01047 ,  H01L2924/053 ,  H01L2924/049 ,  H01L2924/06 ,  H01L2924/04953

Abstract: The present technology is directed to manufacturing collars for under-bump metal (UBM) structures for die-to-die and/or package-to-package interconnects and associated systems. A semiconductor die includes a semiconductor material having solid-state components and an interconnect extending at least partially through the semiconductor material. An under-bump metal (UBM) structure is formed over the semiconductor material and is electrically coupled to corresponding interconnects. A collar surrounds at least a portion of the side surface of the UBM structure, and a solder material is disposed over the top surface of the UBM structure.

公开(公告)号：US20170287857A1

公开(公告)日：2017-10-05

申请号：US15624493

申请日：2017-06-15

Applicant: Micron Technology, Inc.

Inventor： Brandon P. Wirz ,  Jaspreet S. Gandhi ,  Christopher J. Gambee ,  Satish Yeldandi

IPC: H01L23/00 ,  H01L23/48

CPC classification number: H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/94 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0347 ,  H01L2224/03614 ,  H01L2224/038 ,  H01L2224/0382 ,  H01L2224/039 ,  H01L2224/03914 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05016 ,  H01L2224/05017 ,  H01L2224/05025 ,  H01L2224/0508 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05187 ,  H01L2224/05583 ,  H01L2224/05584 ,  H01L2224/05687 ,  H01L2224/94 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/365 ,  H01L2924/00014 ,  H01L2924/04953 ,  H01L2924/01074 ,  H01L2924/00012 ,  H01L2924/053 ,  H01L2924/054 ,  H01L2224/03

Abstract: The present technology is directed to manufacturing semiconductor dies with under-bump metal (UBM) structures for die-to-die and/or package-to-package interconnects or other types of interconnects. In one embodiment, a method for forming under-bump metal (UBM) structures on a semiconductor die comprises constructing a UBM pillar by plating a first material onto first areas of a seed structure and depositing a second material over the first material. The first material has first electrical potential and the second material has a second electrical potential greater than the first electrical potential. The method further comprises reducing the difference in the electrical potential between the first material and the second material, and then removing second areas of the seed structure between the UBM pillars thereby forming UBM structures on the semiconductor die.

公开(公告)号：US09711937B2

公开(公告)日：2017-07-18

申请号：US14873080

申请日：2015-10-01

Applicant: SpectraSensors, Inc.

Inventor： Alfred Feitisch ,  Gabi Neubauer ,  Mathias Schrempel

IPC: H01S3/04 ,  H01S5/022 ,  H01L23/00 ,  H01S5/042

CPC classification number: H01S5/02272 ,  H01L24/03 ,  H01L24/05 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L2224/0383 ,  H01L2224/04026 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/05663 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/05669 ,  H01L2224/0567 ,  H01L2224/0568 ,  H01L2224/05681 ,  H01L2224/05684 ,  H01L2224/05686 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/32245 ,  H01L2224/83801 ,  H01L2924/12042 ,  H01L2924/15747 ,  H01S5/02212 ,  H01S5/0425 ,  H01L2924/04941 ,  H01L2924/01022 ,  H01L2924/053 ,  H01L2924/049 ,  H01L2924/00014 ,  H01L2924/01032 ,  H01L2924/01014 ,  H01L2924/014 ,  H01L2924/0105 ,  H01L2924/01029 ,  H01L2924/01082 ,  H01L2924/00

Abstract: A first contact surface of a semiconductor laser chip can be formed to a target surface roughness selected to have a maximum peak to valley height that is substantially smaller than a barrier layer thickness. A barrier layer that includes a non-metallic, electrically-conducting compound and that has the barrier layer thickness can be applied to the first contact surface, and the semiconductor laser chip can be soldered to a carrier mounting along the first contact surface using a solder composition by heating the soldering composition to less than a threshold temperature at which dissolution of the barrier layer into the soldering composition occurs. Related systems, methods, articles of manufacture, and the like are also described.

公开(公告)号：US09673167B2

公开(公告)日：2017-06-06

申请号：US14416297

申请日：2012-07-26

Applicant: Markus Wimplinger

Inventor： Markus Wimplinger

IPC: H01L23/00 ,  H01L31/18 ,  B32B37/24 ,  B32B38/00 ,  C23C14/08 ,  C23C16/40

CPC classification number: H01L24/83 ,  B32B37/24 ,  B32B38/0008 ,  B32B2037/243 ,  B32B2037/246 ,  B32B2457/14 ,  C23C14/08 ,  C23C14/081 ,  C23C14/086 ,  C23C16/40 ,  C23C16/403 ,  C23C16/407 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/75 ,  H01L31/18 ,  H01L2224/2741 ,  H01L2224/27418 ,  H01L2224/2745 ,  H01L2224/27452 ,  H01L2224/278 ,  H01L2224/27848 ,  H01L2224/2908 ,  H01L2224/29187 ,  H01L2224/29287 ,  H01L2224/29394 ,  H01L2224/29395 ,  H01L2224/3201 ,  H01L2224/32145 ,  H01L2224/32501 ,  H01L2224/7501 ,  H01L2224/75101 ,  H01L2224/83001 ,  H01L2224/83002 ,  H01L2224/83011 ,  H01L2224/83012 ,  H01L2224/83013 ,  H01L2224/83065 ,  H01L2224/83075 ,  H01L2224/8322 ,  H01L2224/8383 ,  H01L2224/83896 ,  H01L2224/83907 ,  H01L2924/01009 ,  H01L2924/01013 ,  H01L2924/0103 ,  H01L2924/01031 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/053 ,  H01L2924/12042 ,  H01L2924/20102 ,  H01L2924/0549 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/0531 ,  H01L2924/01001 ,  H01L2924/01008 ,  H01L2924/00

Abstract: This invention relates to a method for bonding of a first contact area of a first at least largely transparent substrate to a second contact area of a second at least largely transparent substrate, on at least one of the contact areas an oxide being used for bonding, from which an at least largely transparent interconnection layer is formed with an electrical conductivity of at least 10e1 S/cm2 (measurement: four point method, relative to temperature of 300K) and an optical transmittance greater than 0.8 (for a wavelength range from 400 nm to 1500 nm) on the first and second contact area.

公开(公告)号：US09576922B2

公开(公告)日：2017-02-21

申请号：US14702984

申请日：2015-05-04

Applicant: GLOBALFOUNDRIES INC.

Inventor： Thomas J. Brunschwiler ,  Eric D. Perfecto ,  Jonas Zuercher

IPC: H01L23/00 ,  B23K1/00 ,  B23K31/02

CPC classification number: H01L24/10 ,  B23K1/0016 ,  B23K1/0053 ,  B23K1/008 ,  B23K1/012 ,  B23K1/20 ,  B23K31/02 ,  B23K35/02 ,  B23K2101/42 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/26 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/10175 ,  H01L2224/1132 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13294 ,  H01L2224/133 ,  H01L2224/13639 ,  H01L2224/13644 ,  H01L2224/13647 ,  H01L2224/13687 ,  H01L2224/16227 ,  H01L2224/16505 ,  H01L2224/2929 ,  H01L2224/29387 ,  H01L2224/32225 ,  H01L2224/812 ,  H01L2224/81203 ,  H01L2224/8121 ,  H01L2224/8123 ,  H01L2224/81815 ,  H01L2224/81909 ,  H01L2224/81911 ,  H01L2224/8192 ,  H01L2224/81986 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2924/01322 ,  H01L2924/07025 ,  H01L2924/3651 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/00012 ,  H01L2924/053 ,  H01L2924/0665 ,  H01L2924/05442 ,  H01L2224/81948

Abstract: A method of forming a stacked surface arrangement for semiconductor devices includes joining a first surface to a second surface with a solder bump, the solder bump including a substantially pure first metal; depositing nanoparticles of a second metal onto a surface of the solder bump; performing an annealing operation to form a film of the second metal on the surface of the solder bump; and performing a reflow or a second annealing operation to transform the solder bump from the substantially pure first metal to an alloy of the first metal and the second metal.

Abstract translation: 一种形成用于半导体器件的堆叠表面布置的方法包括：将第一表面与第二表面焊接在一起，所述焊料凸块包括基本上纯的第一金属; 将第二金属的纳米颗粒沉积到所述焊料凸块的表面上; 执行退火操作以在所述焊料凸块的表面上形成所述第二金属的膜; 以及执行回流或第二退火操作以将焊料凸块从基本上纯的第一金属转变为第一金属和第二金属的合金。

公开(公告)号：US20160343762A1

公开(公告)日：2016-11-24

申请号：US15228860

申请日：2016-08-04

Applicant: Sony Corporation

Inventor： Yoshihisa Kagawa ,  Kenichi Aoyagi ,  Yoshiya Hagimoto ,  Nobutoshi Fujii

IPC: H01L27/146

CPC classification number: H01L27/14636 ,  H01L21/76807 ,  H01L21/7684 ,  H01L21/76841 ,  H01L21/76843 ,  H01L23/481 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53295 ,  H01L23/564 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/80 ,  H01L24/83 ,  H01L27/0688 ,  H01L27/14609 ,  H01L27/14621 ,  H01L27/14625 ,  H01L27/1464 ,  H01L27/14645 ,  H01L27/1469 ,  H01L2221/1031 ,  H01L2224/02245 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05546 ,  H01L2224/05547 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05578 ,  H01L2224/05647 ,  H01L2224/05686 ,  H01L2224/08121 ,  H01L2224/08145 ,  H01L2224/0903 ,  H01L2224/80011 ,  H01L2224/80013 ,  H01L2224/80091 ,  H01L2224/80097 ,  H01L2224/80203 ,  H01L2224/80345 ,  H01L2224/80357 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/83345 ,  H01L2924/00014 ,  H01L2924/12043 ,  H01L2924/13091 ,  H04N5/369 ,  H01L2924/00012 ,  H01L2924/05442 ,  H01L2924/05042 ,  H01L2924/053 ,  H01L2924/049 ,  H01L2924/00 ,  H01L2224/05552

Abstract: Disclosed herein is a semiconductor device, including: a first substrate including a first electrode, and a first insulating film configured from a diffusion preventing material for the first electrode and covering a periphery of the first electrode, the first electrode and the first insulating film cooperating with each other to configure a bonding face; and a second substrate bonded to and provided on the first substrate and including a second electrode joined to the first electrode, and a second insulating film configured from a diffusion preventing material for the second electrode and covering a periphery of the second electrode, the second electrode and the second insulating film cooperating with each other to configure a bonding face to the first substrate.

公开(公告)号：US20160329289A1

公开(公告)日：2016-11-10

申请号：US14702984

申请日：2015-05-04

Applicant: GLOBALFOUNDRIES INC.

Inventor： Thomas J. Brunschwiler ,  Eric D. Perfecto ,  Jonas Zuercher

IPC: H01L23/00 ,  B23K31/02 ,  B23K1/00

CPC classification number: H01L24/10 ,  B23K1/0016 ,  B23K1/0053 ,  B23K1/008 ,  B23K1/012 ,  B23K1/20 ,  B23K31/02 ,  B23K35/02 ,  B23K2101/42 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/26 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/10175 ,  H01L2224/1132 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13294 ,  H01L2224/133 ,  H01L2224/13639 ,  H01L2224/13644 ,  H01L2224/13647 ,  H01L2224/13687 ,  H01L2224/16227 ,  H01L2224/16505 ,  H01L2224/2929 ,  H01L2224/29387 ,  H01L2224/32225 ,  H01L2224/812 ,  H01L2224/81203 ,  H01L2224/8121 ,  H01L2224/8123 ,  H01L2224/81815 ,  H01L2224/81909 ,  H01L2224/81911 ,  H01L2224/8192 ,  H01L2224/81986 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2924/01322 ,  H01L2924/07025 ,  H01L2924/3651 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/00012 ,  H01L2924/053 ,  H01L2924/0665 ,  H01L2924/05442 ,  H01L2224/81948

Abstract: A method of forming a stacked surface arrangement for semiconductor devices includes joining a first surface to a second surface with a solder bump, the solder bump including a substantially pure first metal; depositing nanoparticles of a second metal onto a surface of the solder bump; performing an annealing operation to form a film of the second metal on the surface of the solder bump; and performing a reflow or a second annealing operation to transform the solder bump from the substantially pure first metal to an alloy of the first metal and the second metal.

Abstract translation: 一种形成用于半导体器件的堆叠表面布置的方法包括：将第一表面与第二表面焊接在一起，所述焊料凸块包括基本上纯的第一金属; 将第二金属的纳米颗粒沉积到所述焊料凸块的表面上; 执行退火操作以在所述焊料凸块的表面上形成所述第二金属的膜; 以及执行回流或第二退火操作以将焊料凸块从基本上纯的第一金属转变为第一金属和第二金属的合金。

公开(公告)号：US09466719B2

公开(公告)日：2016-10-11

申请号：US14540268

申请日：2014-11-13

Applicant: QUALCOMM SWITCH CORP.

Inventor： Paul A. Nygaard ,  Stuart B. Molin ,  Michael A. Stuber ,  Max Aubain

IPC: H01L21/78 ,  H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L21/84 ,  H01L23/36 ,  H01L23/367 ,  H01L29/786 ,  H01L27/12 ,  H01L23/00 ,  H01L21/762

CPC classification number: H01L29/1054 ,  H01L21/76256 ,  H01L21/78 ,  H01L21/84 ,  H01L23/36 ,  H01L23/3675 ,  H01L23/3677 ,  H01L24/03 ,  H01L24/08 ,  H01L24/11 ,  H01L24/13 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/80 ,  H01L24/83 ,  H01L24/94 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/1033 ,  H01L29/78 ,  H01L29/7843 ,  H01L29/7849 ,  H01L29/78603 ,  H01L29/78606 ,  H01L29/78654 ,  H01L2221/6834 ,  H01L2221/6835 ,  H01L2221/68377 ,  H01L2224/03845 ,  H01L2224/05572 ,  H01L2224/08225 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/29186 ,  H01L2224/29188 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/48 ,  H01L2224/80006 ,  H01L2224/8022 ,  H01L2224/80801 ,  H01L2224/80894 ,  H01L2224/83005 ,  H01L2224/8322 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/9202 ,  H01L2224/9212 ,  H01L2224/92142 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/1305 ,  H01L2924/3011 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2924/053 ,  H01L2924/00012 ,  H01L2224/83 ,  H01L2224/80 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2224/45099

Abstract: Embodiments of the present invention provide for the enhancement of transistors in a semiconductor structure using a strain layer. The structure comprises a patterned layer consisting of an excavated region and a pattern region, a strain layer located in the excavated region and on the pattern region, an active layer located above the strain layer, a field effect transistor formed in the active layer, and a handle layer located above the active layer. The field effect transistor comprises a source, a drain, and a channel. The channel lies completely within a lateral extent of the pattern region. The source and the drain each lie only partially within the lateral extent of the pattern region. The strain layer alters a carrier mobility of the channel. In some embodiments, the strain layer is introduced to the back side of a semiconductor-on-insulator structure.

Abstract translation: 本发明的实施例提供了使用应变层的半导体结构中的晶体管的增强。 该结构包括由挖掘区域和图案区域构成的图案层，位于挖掘区域和图案区域上的应变层，位于应变层上方的有源层，形成在有源层中的场效应晶体管，以及 位于有源层上方的手柄层。 场效应晶体管包括源极，漏极和沟道。 通道完全位于图案区域的横向范围内。 源极和漏极各自仅部分地位于图案区域的横向范围内。 应变层改变通道的载流子迁移率。 在一些实施例中，将应变层引入到绝缘体上半导体结构的背面。

公开(公告)号：US20160168351A1

公开(公告)日：2016-06-16

申请号：US15047866

申请日：2016-02-19

Applicant: Intel Corporation

Inventor： Yonghao Xiu ,  Nisha Ananthakrishnan ,  Yiqun Bai ,  Arjun Krishnan

IPC: C08K3/00 ,  H01L23/29 ,  H01L21/56

CPC classification number: C08K3/013 ,  H01L21/563 ,  H01L23/295 ,  H01L24/17 ,  H01L24/29 ,  H01L24/81 ,  H01L24/83 ,  H01L24/91 ,  H01L2224/131 ,  H01L2224/16057 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/2929 ,  H01L2224/29386 ,  H01L2224/29499 ,  H01L2224/73204 ,  H01L2224/81801 ,  H01L2224/83102 ,  H01L2924/01006 ,  H01L2924/04642 ,  H01L2924/0493 ,  H01L2924/053 ,  H01L2924/0533 ,  H01L2924/05341 ,  H01L2924/05432 ,  H01L2924/05442 ,  H01L2924/186 ,  H01L2924/0665 ,  H01L2924/05032 ,  H01L2924/014

Abstract: An underfill composition comprises a curable resin, a plurality of filler particles loaded within the resin, the filler particles comprising at least 50 weight % of the underfill composition. The filler particles comprise first filler particles having a particle size of from 0.1 micrometers to 15 micrometers and second filler particles having a particle size of less than 100 nanometers. A viscosity of the underfill composition is less than a viscosity of a corresponding composition not including the second filler particles.