公开(公告)号：US20180182696A1

公开(公告)日：2018-06-28

申请号：US15900696

申请日：2018-02-20

申请人： INTEL CORPORATION

发明人： Sanka GANESAN ,  Zhiguo QIAN ,  Robert L. SANKMAN ,  Krishna SRINIVASAN ,  Zhaohui ZHU

IPC分类号： H01L23/498 ,  H01L23/50 ,  H01L21/768 ,  H01L23/00 ,  H01L23/538

CPC分类号： H01L23/49811 ,  H01L21/76885 ,  H01L23/50 ,  H01L23/5386 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/10126 ,  H01L2224/1147 ,  H01L2224/1182 ,  H01L2224/11831 ,  H01L2224/11849 ,  H01L2224/1301 ,  H01L2224/13013 ,  H01L2224/13014 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13562 ,  H01L2224/1357 ,  H01L2224/13687 ,  H01L2224/14132 ,  H01L2224/14133 ,  H01L2224/14135 ,  H01L2224/14136 ,  H01L2224/16013 ,  H01L2224/16014 ,  H01L2224/16058 ,  H01L2224/16238 ,  H01L2224/1703 ,  H01L2224/17051 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81385 ,  H01L2224/81395 ,  H01L2224/81411 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81815 ,  H01L2924/05042 ,  H01L2924/1434 ,  H01L2924/381 ,  H01L2924/3841 ,  H01L2924/014 ,  H01L2924/00014

摘要： Electronic assemblies and methods including the formation of interconnect structures are described. In one embodiment an apparatus includes semiconductor die and a first metal bump on the die, the first metal bump including a surface having a first part and a second part. The apparatus also includes a solder resistant coating covering the first part of the surface and leaving the second part of the surface uncovered. Other embodiments are described and claimed.

公开(公告)号：US20170345738A1

公开(公告)日：2017-11-30

申请号：US15167640

申请日：2016-05-27

申请人： International Business Machines Corporation

发明人： Daniel C Edelstein ,  Chih-Chao Yang

IPC分类号： H01L23/48 ,  H01L21/768 ,  H01L23/532

CPC分类号： H01L23/481 ,  H01L21/76856 ,  H01L21/76873 ,  H01L21/76898 ,  H01L21/8221 ,  H01L23/53238 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/92 ,  H01L24/94 ,  H01L25/065 ,  H01L27/0688 ,  H01L2224/04 ,  H01L2224/04026 ,  H01L2224/05009 ,  H01L2224/05576 ,  H01L2224/05647 ,  H01L2224/05687 ,  H01L2224/06102 ,  H01L2224/08146 ,  H01L2224/13009 ,  H01L2224/13147 ,  H01L2224/13565 ,  H01L2224/13583 ,  H01L2224/13657 ,  H01L2224/13666 ,  H01L2224/13673 ,  H01L2224/13676 ,  H01L2224/13681 ,  H01L2224/13684 ,  H01L2224/13687 ,  H01L2224/29006 ,  H01L2224/29187 ,  H01L2224/32146 ,  H01L2224/73204 ,  H01L2224/9211 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/05442 ,  H01L2224/83 ,  H01L2924/04953 ,  H01L2924/04941 ,  H01L2924/0496 ,  H01L2924/01074 ,  H01L2924/0499 ,  H01L2924/01027 ,  H01L2924/0498 ,  H01L2924/01044 ,  H01L2224/08 ,  H01L2224/80 ,  H01L2224/81

摘要： A method providing a high aspect ratio through substrate via in a substrate is described. The through substrate via has vertical sidewalls and a horizontal bottom. The substrate has a horizontal field area surrounding the through substrate via. A first metallic barrier layer is deposited on the sidewalls of the through substrate via. A nitridation process converts a surface portion of the metallic barrier layer to a nitride surface layer. The nitride surface layer enhances the nucleation of subsequent depositions. A first metal layer is deposited to fill the through substrate via. A selective etch creates a recess in the first metal layer in the through substrate via. A second barrier layer is deposited over the recess. A second metal layer is patterned over the second barrier layer filling the recess and creating a contact. Another aspect of the invention is a device produced by the method.

公开(公告)号：US09779965B2

公开(公告)日：2017-10-03

申请号：US15456767

申请日：2017-03-13

申请人： Kulicke and Soffa Industries, Inc.

发明人： Robert N. Chylak ,  Dominick A. DeAngelis ,  Horst Clauberg

IPC分类号： H01L21/449 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L21/762 ,  H01L21/60

CPC分类号： H01L21/449 ,  H01L21/76251 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/48 ,  H01L24/75 ,  H01L24/81 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2021/60195 ,  H01L2224/1134 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13109 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13187 ,  H01L2224/136 ,  H01L2224/13687 ,  H01L2224/16148 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/48091 ,  H01L2224/48225 ,  H01L2224/75251 ,  H01L2224/75252 ,  H01L2224/75301 ,  H01L2224/75343 ,  H01L2224/75348 ,  H01L2224/75349 ,  H01L2224/75744 ,  H01L2224/75745 ,  H01L2224/759 ,  H01L2224/81121 ,  H01L2224/81193 ,  H01L2224/81201 ,  H01L2224/81203 ,  H01L2224/81205 ,  H01L2224/81207 ,  H01L2224/81355 ,  H01L2224/81409 ,  H01L2224/81424 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81801 ,  H01L2224/81895 ,  H01L2224/81906 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/20102 ,  H01L2924/20103 ,  H01L2924/20104 ,  H01L2924/20105 ,  H01L2924/20106 ,  H01L2924/20107 ,  H01L2924/20301 ,  H01L2924/20302 ,  H01L2924/20303 ,  H01L2924/20304 ,  H01L2924/20305 ,  H01L2924/20306 ,  H01L2924/20307 ,  H01L2924/01029 ,  H01L2924/01014 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/8121 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/81 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/0503 ,  H01L2924/01013 ,  H01L2924/0504 ,  H01L2924/0105 ,  H01L2924/0502 ,  H01L2924/0103 ,  H01L2924/0494 ,  H01L2924/0104 ,  H01L2924/0495 ,  H01L2924/01023 ,  H01L2924/0496 ,  H01L2924/01024 ,  H01L2924/05 ,  H01L2924/01028 ,  H01L2924/0543 ,  H01L2924/0544 ,  H01L2924/0542 ,  H01L2924/0534 ,  H01L2924/0535 ,  H01L2924/0536 ,  H01L2924/054 ,  H01L2924/0463 ,  H01L2924/0464 ,  H01L2924/0462 ,  H01L2924/0454 ,  H01L2924/0455 ,  H01L2924/0456 ,  H01L2924/046 ,  H01L2924/01105

摘要： A method of ultrasonically bonding semiconductor elements includes the steps of: (a) aligning surfaces of a plurality of first conductive structures of a first semiconductor element to respective surfaces of a plurality of second conductive structures of a second semiconductor element; and (b) ultrasonically bonding ones of the first conductive structures to respective ones of the second conductive structures. A bonding surface of at least one of the first conductive structures and the second conductive structures includes a frangible coating.

公开(公告)号：US20170252871A1

公开(公告)日：2017-09-07

申请号：US15327510

申请日：2014-08-29

申请人： Senju Metal Industry Co., Ltd.

发明人： Hiroyoshi Kawasaki ,  Takahiro Roppongi ,  Daisuke Soma ,  Isamu Sato ,  Yuji Kawamata

IPC分类号： B23K35/02 ,  H01L23/00 ,  C23C8/10 ,  C22C13/00 ,  B23K35/26 ,  B23K35/365

CPC分类号： B23K35/0244 ,  B22F1/02 ,  B22F2999/00 ,  B23K35/26 ,  B23K35/262 ,  B23K35/365 ,  C22C13/00 ,  C23C8/10 ,  C23C8/36 ,  C23C28/04 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/11318 ,  H01L2224/1182 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/1312 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13157 ,  H01L2224/1316 ,  H01L2224/13561 ,  H01L2224/13687 ,  H01L2924/0105 ,  H01L2924/014 ,  H01L2924/0544 ,  C22C1/0483

摘要： Provided is a solder material which enables a growth of an oxide film to be inhibited. A solder ball which is a solder material is composed of a solder layer and a covering layer covering the solder layer. The solder layer is spherical and is composed of a metal material containing an alloy including Sn content of 40% and more. Otherwise the solder layer is composed of a metal material including Sn content of 100%. In the covering layer, a SnO film is formed outside the solder layer, and a SnO2 film is formed outside the SnO film. A thickness of the covering layer is preferably more than 0 nm and equal to or less than 4.5 nm. Additionally, a yellow chromaticity of the solder ball is preferably equal to or less than 5.7.

公开(公告)号：US20170186681A1

公开(公告)日：2017-06-29

申请号：US15459648

申请日：2017-03-15

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Kuo Lung Pan ,  Yu-Feng Chen ,  Chen-Shien Chen

IPC分类号： H01L23/498 ,  H01L25/00 ,  H01L25/065 ,  H01L21/56 ,  H01L21/48

CPC分类号： H01L23/49838 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/563 ,  H01L23/147 ,  H01L23/3157 ,  H01L23/49827 ,  H01L23/49866 ,  H01L23/49894 ,  H01L23/5384 ,  H01L24/05 ,  H01L24/17 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/02245 ,  H01L2224/02251 ,  H01L2224/0226 ,  H01L2224/10175 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13687 ,  H01L2224/1411 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/26145 ,  H01L2224/26175 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81007 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81805 ,  H01L2224/81815 ,  H01L2224/92125 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2924/01029 ,  H01L2924/05042 ,  H01L2924/0541 ,  H01L2924/014 ,  H01L2924/00014

摘要： An example method includes providing a packaging device includes a substrate having an integrated circuit die mounting region. A plurality of microstructures, each including an outer insulating layer over a conductive material, are disposed proximate a side of the integrated circuit die mounting region. An underfill material is disposed between the substrate and the integrated circuit die, the microstructures preventing spread of the underfill. In another example method, a via can be formed in a substrate and the substrate etched to form a bump or pillar from the via. An insulating material can be formed over the bump or pillar. In another example method, a photoresist deposited over a seed layer and patterned to form openings. A conductive material is plated in the openings, forming a plurality of pillars or bumps. The photoresist and exposed seed layer are removed. The conductive material is oxidized to form an insulating material.

公开(公告)号：US08823167B2

公开(公告)日：2014-09-02

申请号：US13551421

申请日：2012-07-17

申请人： Yi-Wen Wu ,  Cheng-Chung Lin ,  Chien Ling Hwang ,  Chung-Shi Liu

发明人： Yi-Wen Wu ,  Cheng-Chung Lin ,  Chien Ling Hwang ,  Chung-Shi Liu

IPC分类号： H01L23/48 ,  H01L23/52

CPC分类号： H01L23/49811 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/0345 ,  H01L2224/0401 ,  H01L2224/05023 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05187 ,  H01L2224/05541 ,  H01L2224/05568 ,  H01L2224/05582 ,  H01L2224/05611 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/05681 ,  H01L2224/05687 ,  H01L2224/10145 ,  H01L2224/11002 ,  H01L2224/1112 ,  H01L2224/1132 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/1147 ,  H01L2224/11827 ,  H01L2224/11831 ,  H01L2224/11849 ,  H01L2224/11912 ,  H01L2224/13005 ,  H01L2224/13007 ,  H01L2224/13023 ,  H01L2224/13083 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13118 ,  H01L2224/1312 ,  H01L2224/13123 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13166 ,  H01L2224/13169 ,  H01L2224/1317 ,  H01L2224/13171 ,  H01L2224/13181 ,  H01L2224/13551 ,  H01L2224/13561 ,  H01L2224/13565 ,  H01L2224/1357 ,  H01L2224/1358 ,  H01L2224/13582 ,  H01L2224/13644 ,  H01L2224/13647 ,  H01L2224/13655 ,  H01L2224/13664 ,  H01L2224/13686 ,  H01L2224/13687 ,  H01L2224/13688 ,  H01L2224/1369 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/814 ,  H01L2224/81815 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01025 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/0104 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/05442 ,  H01L2924/0665 ,  H01L2924/07025 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/3841 ,  H01L2924/0105 ,  H01L2224/11 ,  H01L2924/01007 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/00 ,  H01L2224/05552

摘要： This description relates to an integrated circuit device including a conductive pillar formed over a substrate. The conductive pillar has a sidewall surface and a top surface. The integrated circuit device further includes an under-bump-metallurgy (UBM) layer between the substrate and the conductive pillar. The UBM layer has a surface region. The integrated circuit device further includes a protection structure on the sidewall surface of the conductive pillar and the surface region of the UBM layer. The protection structure is formed of a non-metal material.

摘要翻译： 该描述涉及一种集成电路器件，其包括形成在衬底上的导电柱。 导电柱具有侧壁表面和顶表面。 集成电路器件还包括在衬底和导电柱之间的凸起下 - 冶金（UBM）层。 UBM层具有表面区域。 集成电路装置还包括在导电柱的侧壁表面和UBM层的表面区域上的保护结构。 保护结构由非金属材料形成。

公开(公告)号：US20120068355A1

公开(公告)日：2012-03-22

申请号：US13178470

申请日：2011-07-07

申请人： Mayu Aoki ,  Kenichi Takeda ,  Kazuyuki Hozawa

发明人： Mayu Aoki ,  Kenichi Takeda ,  Kazuyuki Hozawa

IPC分类号： H01L23/48 ,  H01L21/28

CPC分类号： H01L25/50 ,  H01L23/481 ,  H01L23/562 ,  H01L24/05 ,  H01L24/08 ,  H01L24/13 ,  H01L24/29 ,  H01L24/80 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/05547 ,  H01L2224/05557 ,  H01L2224/08121 ,  H01L2224/11462 ,  H01L2224/1148 ,  H01L2224/11602 ,  H01L2224/13019 ,  H01L2224/13147 ,  H01L2224/13565 ,  H01L2224/13582 ,  H01L2224/13647 ,  H01L2224/13687 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/26122 ,  H01L2224/2919 ,  H01L2224/73104 ,  H01L2224/81007 ,  H01L2224/81203 ,  H01L2224/83007 ,  H01L2224/83203 ,  H01L2224/83862 ,  H01L2224/9211 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2924/00013 ,  H01L2924/01029 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2224/11 ,  H01L2924/00014 ,  H01L2924/04941 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/13099 ,  H01L2224/05099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00

摘要： A semiconductor device including two silicon wafers stacked and bonded together with bumps of one wafer electrically coupled with those of the other wafer, in which generation of voids on the junction surface between the silicon wafers is suppressed. Due to a recess made in the surface of a buried conductive film, a cavity is formed in the junction surface between the silicon wafers. The ends of the cavity extend to the periphery of the junction surface between the silicon wafers. This allows the air trapped on the junction surface between the silicon wafers to get out through the cavity, thereby reducing the possibility of generation of voids on the junction surface.

摘要翻译： 一种半导体器件，包括两个硅晶片，其叠置并与由另一个晶片电耦合的一个晶片的凸块结合在一起，其中硅晶片之间的接合表面上的空隙产生被抑制。 由于在掩埋导电膜的表面上形成的凹部，在硅晶片之间的接合表面中形成空腔。 腔的端部延伸到硅晶片之间的接合表面的周边。 这允许捕获在硅晶片之间的接合表面上的空气通过空腔排出，从而减少在接合表面上产生空隙的可能性。

公开(公告)号：US07781260B2

公开(公告)日：2010-08-24

申请号：US11853752

申请日：2007-09-11

申请人： Sandeep Sane ,  Nachiket Raravikar

发明人： Sandeep Sane ,  Nachiket Raravikar

IPC分类号： H01L21/44 ,  H01L21/48

CPC分类号： H01L21/563 ,  H01L23/291 ,  H01L23/293 ,  H01L23/3157 ,  H01L24/11 ,  H01L24/13 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/1182 ,  H01L2224/11827 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13687 ,  H01L2224/13693 ,  H01L2224/16225 ,  H01L2224/165 ,  H01L2224/2919 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/814 ,  H01L2224/8192 ,  H01L2224/81948 ,  H01L2224/831 ,  H01L2224/83379 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/3512

摘要： Methods and associated structures of forming microelectronic devices are described. Those methods may include coating an interconnect structure disposed on a die with a layer of functionalized nanoparticles, wherein the functionalized nanoparticles are dispersed in a solvent, heating the layer of functionalized nanoparticles to drive off a portion of the solvent, and applying an underfill on the coated interconnect structure.

摘要翻译： 描述形成微电子器件的方法和相关结构。 这些方法可以包括用功能化纳米颗粒层涂布设置在管芯上的互连结构，其中官能化纳米颗粒分散在溶剂中，加热功能化纳米颗粒层以驱除溶剂的一部分，并将底部填充物 涂层互连结构。

公开(公告)号：US07186637B2

公开(公告)日：2007-03-06

申请号：US10631508

申请日：2003-07-31

申请人： Grant Kloster ,  Shriram Ramanathan ,  Chin-Chang Chen ,  Paul Fischer

发明人： Grant Kloster ,  Shriram Ramanathan ,  Chin-Chang Chen ,  Paul Fischer

IPC分类号： H10L21/44 ,  H10L23/52 ,  H10L23/48 ,  H10L23/40 ,  H10L23/485

CPC分类号： H01L21/76251 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/05684 ,  H01L2224/1146 ,  H01L2224/1148 ,  H01L2224/11825 ,  H01L2224/11826 ,  H01L2224/13022 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13157 ,  H01L2224/13166 ,  H01L2224/13171 ,  H01L2224/13184 ,  H01L2224/13562 ,  H01L2224/13565 ,  H01L2224/1357 ,  H01L2224/13578 ,  H01L2224/13624 ,  H01L2224/13657 ,  H01L2224/13666 ,  H01L2224/13681 ,  H01L2224/13684 ,  H01L2224/13687 ,  H01L2224/81097 ,  H01L2224/81193 ,  H01L2224/81895 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  Y10T29/49128 ,  Y10T428/24917 ,  H01L2924/00014

摘要： A method of bonding semiconductor devices is disclosed. The method comprises providing a first substrate having a first conductive interconnecting structure formed thereon and a second substrate having a second conductive interconnecting structure formed thereon. A first conductive passivation layer is selectively formed over exposed areas of the first conductive interconnecting structure. A second conductive passivation layer is selectively formed over exposed areas of the second conductive interconnecting structure. The first substrate and the second substrate are bonded together in such a way that the first conductive passivation layer bonds to the second conductive passivation layer to create a passivation-passivation interface.

摘要翻译： 公开了半导体器件的接合方法。 该方法包括提供其上形成有第一导电互连结构的第一基板和在其上形成有第二导电互连结构的第二基板。 在第一导电互连结构的暴露区域上选择性地形成第一导电钝化层。 在第二导电互连结构的暴露区域上有选择地形成第二导电钝化层。 第一衬底和第二衬底以这样的方式结合在一起，使得第一导电钝化层结合到第二导电钝化层以产生钝化钝化界面。

公开(公告)号：US20240006360A1

公开(公告)日：2024-01-04

申请号：US17853978

申请日：2022-06-30

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Hsih-Yang CHIU

IPC分类号： H01L23/00

CPC分类号： H01L24/13 ,  H01L24/16 ,  H01L24/11 ,  H01L24/81 ,  H01L2224/16148 ,  H01L2224/81203 ,  H01L2224/11622 ,  H01L2224/11462 ,  H01L2224/13147 ,  H01L2224/13007 ,  H01L2224/13541 ,  H01L2224/13553 ,  H01L2224/13561 ,  H01L2224/1358 ,  H01L2224/13687 ,  H01L24/05 ,  H01L2224/05624 ,  H01L2224/05555 ,  H01L2224/13666 ,  H01L2224/13647 ,  H01L2224/13611 ,  H01L2224/13639 ,  H01L2224/13014 ,  H01L2924/3841

摘要： The present application provides a semiconductor structure having a copper pillar within a solder bump, and a manufacturing method of the semiconductor structure. The semiconductor structure includes a substrate having a pad disposed thereon and a passivation at least partially surrounding the pad; and a conductive bump structure disposed over the passivation and the pad, wherein the conductive bump structure includes a first bump portion disposed over the passivation and the pad, a conductive pillar disposed over the first bump portion, and a second bump portion disposed over and surrounding the conductive pillar.