公开(公告)号：US20240113066A1

公开(公告)日：2024-04-04

申请号：US18264719

申请日：2022-01-28

Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION

Inventor： Takashi IMAHIGASHI

IPC: H01L23/00 ,  H01S5/0234 ,  H01S5/026

CPC classification number: H01L24/73 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01S5/0234 ,  H01S5/0261 ,  H01L24/11 ,  H01L24/27 ,  H01L2224/05073 ,  H01L2224/05573 ,  H01L2224/05644 ,  H01L2224/1145 ,  H01L2224/11466 ,  H01L2224/1147 ,  H01L2224/11848 ,  H01L2224/13014 ,  H01L2224/13082 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13169 ,  H01L2224/14136 ,  H01L2224/16145 ,  H01L2224/2745 ,  H01L2224/27466 ,  H01L2224/2747 ,  H01L2224/27848 ,  H01L2224/29011 ,  H01L2224/29023 ,  H01L2224/29035 ,  H01L2224/29082 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/29169 ,  H01L2224/32145 ,  H01L2224/73203 ,  H01L2924/01203 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/10335 ,  H01L2924/12042 ,  H01L2924/1426

Abstract: An electronic device according to the present disclosure includes a semiconductor substrate, a chip, a bump, and a sidewall portion. The bump connects a plurality of connection pads provided on the opposing main surfaces of the semiconductor substrate and the chip. The sidewall portion includes a porous metal layer and that annularly surrounds a region where a plurality of bumps is provided, and connects the semiconductor substrate and the chip. The chip has a thermal expansion coefficient different from that of the semiconductor substrate by 0.1 ppm/° C. or more. The chip is a semiconductor laser, and the semiconductor substrate includes a drive circuit that drives the semiconductor laser.

公开(公告)号：US09922916B2

公开(公告)日：2018-03-20

申请号：US15174921

申请日：2016-06-06

Applicant: INTEL CORPORATION

Inventor： Sanka Ganesan ,  Zhiguo Qian ,  Robert L. Sankman ,  Krishna Srinivasan ,  Zhaohui Zhu

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/50 ,  H01L21/768 ,  H01L23/538

CPC classification number: H01L23/49811 ,  H01L21/76885 ,  H01L23/50 ,  H01L23/5386 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/10126 ,  H01L2224/1147 ,  H01L2224/1182 ,  H01L2224/11831 ,  H01L2224/11849 ,  H01L2224/1301 ,  H01L2224/13013 ,  H01L2224/13014 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13562 ,  H01L2224/1357 ,  H01L2224/13687 ,  H01L2224/14132 ,  H01L2224/14133 ,  H01L2224/14135 ,  H01L2224/14136 ,  H01L2224/16013 ,  H01L2224/16014 ,  H01L2224/16058 ,  H01L2224/16238 ,  H01L2224/1703 ,  H01L2224/17051 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81385 ,  H01L2224/81395 ,  H01L2224/81411 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81815 ,  H01L2924/05042 ,  H01L2924/1434 ,  H01L2924/381 ,  H01L2924/3841 ,  H01L2924/014 ,  H01L2924/00014

Abstract: Electronic assemblies and methods including the formation of interconnect structures are described. In one embodiment an apparatus includes semiconductor die and a first metal bump on the die, the first metal bump including a surface having a first part and a second part. The apparatus also includes a solder resistant coating covering the first part of the surface and leaving the second part of the surface uncovered. Other embodiments are described and claimed.

公开(公告)号：US09589921B2

公开(公告)日：2017-03-07

申请号：US14773817

申请日：2014-03-10

Applicant: PS4 Luxco S.a.r.l. ,  Mitsuaki Katagiri ,  Yu Hasegawa ,  Satoshi Isa

Inventor： Mitsuaki Katagiri ,  Yu Hasegawa ,  Satoshi Isa

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/498 ,  H01L25/065 ,  H01L23/12 ,  H01L21/56 ,  H01L21/66 ,  H05K1/02 ,  H05K1/14 ,  H05K1/18

CPC classification number: H01L24/17 ,  H01L21/561 ,  H01L22/32 ,  H01L23/12 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/0235 ,  H01L2224/02375 ,  H01L2224/0345 ,  H01L2224/03912 ,  H01L2224/0392 ,  H01L2224/0401 ,  H01L2224/05014 ,  H01L2224/05015 ,  H01L2224/05025 ,  H01L2224/05166 ,  H01L2224/05548 ,  H01L2224/05554 ,  H01L2224/05647 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/06102 ,  H01L2224/11462 ,  H01L2224/11472 ,  H01L2224/11849 ,  H01L2224/13006 ,  H01L2224/13007 ,  H01L2224/13013 ,  H01L2224/13014 ,  H01L2224/13017 ,  H01L2224/13018 ,  H01L2224/13021 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13025 ,  H01L2224/13028 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/1411 ,  H01L2224/14131 ,  H01L2224/14135 ,  H01L2224/14136 ,  H01L2224/14177 ,  H01L2224/14181 ,  H01L2224/14515 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16148 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/17181 ,  H01L2224/17517 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81801 ,  H01L2224/83102 ,  H01L2224/83862 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06596 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01L2924/3511 ,  H05K1/025 ,  H05K1/141 ,  H05K1/185 ,  H05K2201/10734 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2224/11 ,  H01L2924/014 ,  H01L2924/00

Abstract: In one semiconductor device, a semiconductor chip has first and second pad electrodes disposed on the main surface thereof, insulating films that cover the main surface of the semiconductor chip, a rewiring layer that is disposed between the insulating films, and a plurality of external terminals disposed on the top of the insulating film. The plane size of the first pad electrode and the second pad electrode differ from one another, and the first pad electrode and the second pad electrode are connected to any of the plurality of external terminals via the rewiring layer.

Abstract translation: 在一个半导体器件中，半导体芯片具有设置在其主表面上的第一和第二焊盘电极，覆盖半导体芯片的主表面的绝缘膜，布置在绝缘膜之间的再布线层和多​​个外部端子 设置在绝缘膜的顶部。 第一焊盘电极和第二焊盘电极的平面尺寸彼此不同，并且第一焊盘电极和第二焊盘电极经由重新布线层连接到多个外部端子中的任何一个。

公开(公告)号：US09589915B2

公开(公告)日：2017-03-07

申请号：US14333709

申请日：2014-07-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Tsung-Yuan Yu ,  Hao-Yi Tsai ,  Chao-Wen Shih ,  Wen-Hsin Chan ,  Chen-Chih Hsieh

IPC: H01L23/48 ,  H01L21/60 ,  H01L21/28 ,  H01L23/58 ,  H01L23/10 ,  H01L23/552 ,  H01L23/544 ,  H01L21/56 ,  H01L23/31 ,  H01L23/522 ,  H01L23/00 ,  H01L23/525

CPC classification number: H01L23/585 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/3135 ,  H01L23/3171 ,  H01L23/3192 ,  H01L23/5226 ,  H01L23/525 ,  H01L23/562 ,  H01L24/02 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/94 ,  H01L2224/02377 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/1191 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/14131 ,  H01L2224/14136 ,  H01L2224/16227 ,  H01L2224/94 ,  H01L2924/14 ,  H01L2924/01029 ,  H01L2924/01013 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/0231 ,  H01L2224/11

Abstract: A semiconductor device includes a substrate defined with a seal ring region and a circuit region, the substrate includes a seal ring structure and an integrated circuit structure, the seal ring structure is disposed in the seal ring region and includes a plurality of stacked conductive layers interconnected by a plurality of via layers, the integrated circuit structure is disposed in the circuit region and includes an active or a passive device; a metal pad disposed over the seal ring region and contacted with the seal ring structure; a passivation layer disposed over the substrate and covering the metal pad; a polymeric layer disposed over the passivation layer and the circuit region; and a molding disposed over the passivation layer and the polymeric layer, wherein the seal ring structure is covered by the molding.

Abstract translation: 半导体器件包括限定有密封环区域和电路区域的衬底，所述衬底包括密封环结构和集成电路结构，所述密封环结构设置在所述密封环区域中，并且包括多个互连的层叠导电层 通过多个通孔层，集成电路结构设置在电路区域中并且包括有源或无源器件; 设置在所述密封环区域上并与所述密封环结构接触的金属垫; 钝化层，设置在所述衬底上并覆盖所述金属焊盘; 设置在所述钝化层和所述电路区域上的聚合物层; 以及设置在钝化层和聚合物层上的模制件，其中密封环结构被模制件覆盖。

公开(公告)号：US20170062322A1

公开(公告)日：2017-03-02

申请号：US15207559

申请日：2016-07-12

Applicant: Renesas Electronics Corporation

Inventor： Kazuyuki SAKATA ,  Takafumi BETSUI

IPC: H01L23/498 ,  H01L23/00

CPC classification number: H01L23/49838 ,  H01L21/563 ,  H01L22/32 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/0401 ,  H01L2224/05554 ,  H01L2224/06133 ,  H01L2224/06136 ,  H01L2224/06155 ,  H01L2224/06177 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/14133 ,  H01L2224/14136 ,  H01L2224/14155 ,  H01L2224/16238 ,  H01L2224/32245 ,  H01L2224/48227 ,  H01L2224/49173 ,  H01L2224/49175 ,  H01L2224/49179 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2224/45099

Abstract: A semiconductor device with enhanced reliability. The semiconductor device has a wiring substrate which includes a first terminal electrically connected with a power supply potential supply section of a semiconductor chip, a first wiring coupling the power supply potential supply section with the first terminal, a second terminal electrically connected with a reference potential supply section of the semiconductor chip, and a second wiring coupling the reference potential supply section with the second terminal. The first terminal and second terminal are arranged closer to the periphery of the wiring substrate than the semiconductor chip. The second wiring is extended along the first wiring.

Abstract translation: 具有增强可靠性的半导体器件。 半导体器件具有布线基板，其包括与半导体芯片的电源电位供给部电连接的第一端子，将电源电位供给部与第一端子连接的第一布线，与基准电位电连接的第二端子 半导体芯片的供电部分和将参考电位供应部分与第二端子耦合的第二布线。 第一端子和第二端子比半导体芯片更靠近布线基板的周边布置。 第二个接线沿着第一个接线延伸。

公开(公告)号：US20170025453A1

公开(公告)日：2017-01-26

申请号：US15287636

申请日：2016-10-06

Applicant: FLIR Systems, Inc.

Inventor： Richard E. Bornfreund ,  Joseph H. Durham

IPC: H01L27/146 ,  H01L21/3213 ,  H01L23/544 ,  H01L21/027

CPC classification number: H01L27/1465 ,  H01L21/0272 ,  H01L21/32133 ,  H01L21/32136 ,  H01L23/544 ,  H01L24/11 ,  H01L24/13 ,  H01L27/14634 ,  H01L27/14636 ,  H01L27/14689 ,  H01L27/1469 ,  H01L2223/54426 ,  H01L2224/1147 ,  H01L2224/11622 ,  H01L2224/119 ,  H01L2224/13023 ,  H01L2224/13109 ,  H01L2224/14135 ,  H01L2224/14136 ,  H01L2224/14177 ,  H01L2224/16145 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2924/00014

Abstract: Systems and methods may be provided for coupling together semiconductor devices. One or more of the semiconductor devices may be provided with an array of bump contacts formed in an etch back process. The bump contacts may be indium bumps. The indium bumps may be formed by depositing a sheet of indium onto a surface of a device substrate, depositing and patterning a layer of photoresist over the indium layer, and selectively etching the indium layer to the surface of the substrate using the patterned photoresist layer to form the indium bumps. The substrate may be an infrared detector substrate. The infrared detector substrate may be coupled to a readout integrated circuit substrate using the bumps.

Abstract translation: 可以提供用于将半导体器件耦合在一起的系统和方法。 一个或多个半导体器件可以设置有在回蚀工艺中形成的凸起接触阵列。 凸点触点可以是铟凸块。 铟凸块可以通过将铟片沉积到器件衬底的表面上，在铟层上沉积和图案化光致抗蚀剂层而形成，并且使用图案化的光致抗蚀剂层选择性地将铟层蚀刻到衬底的表面 形成铟凸块。 衬底可以是红外检测器衬底。 红外检测器基板可以使用凸块耦合到读出集成电路基板。

公开(公告)号：US20160111388A1

公开(公告)日：2016-04-21

申请号：US14983753

申请日：2015-12-30

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Shinji Baba ,  Masaki Watanabe ,  Muneharu Tokunaga ,  Kazuyuki Nakagawa

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/29 ,  H01L23/498

CPC classification number: H01L24/17 ,  H01L21/563 ,  H01L23/291 ,  H01L23/3135 ,  H01L23/3142 ,  H01L23/3171 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/14 ,  H01L24/16 ,  H01L24/32 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/1134 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13075 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/14136 ,  H01L2224/14155 ,  H01L2224/14177 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/83102 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/3512 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A technique capable of improving reliability of a semiconductor device is provided. In the present invention, as a wiring board on which a semiconductor chip is mounted, a build-up wiring board is not used but a through wiring board THWB is used. In this manner, in the present invention, the through wiring board formed of only a core layer is used, so that it is not required to consider a difference in thermal expansion coefficient between a build-up layer and the core layer, and besides, it is not required either to consider the electrical disconnection of a fine via formed in the build-up layer because the build-up layer does not exist. As a result, according to the present invention, the reliability of the semiconductor device can be improved while a cost is reduced.

Abstract translation: 提供了能够提高半导体器件的可靠性的技术。 在本发明中，作为安装有半导体芯片的布线基板，不使用积层布线板，而是使用贯通布线板THWB。 以这种方式，在本发明中，仅使用芯层形成的贯通布线板，因此不需要考虑堆积层与芯层之间的热膨胀系数的差异， 不需要考虑由于积聚层不存在而在积层中形成的精细通孔的电断开。 结果，根据本发明，可以提高半导体器件的可靠性，同时降低成本。

公开(公告)号：US08890335B2

公开(公告)日：2014-11-18

申请号：US14132074

申请日：2013-12-18

Applicant: Panasonic Corporation

Inventor： Kenji Yokoyama ,  Takeshi Kawabata

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L24/20 ,  H01L23/49816 ,  H01L23/5286 ,  H01L23/585 ,  H01L24/06 ,  H01L24/14 ,  H01L24/32 ,  H01L24/46 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/02375 ,  H01L2224/02377 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/05554 ,  H01L2224/05568 ,  H01L2224/06155 ,  H01L2224/06156 ,  H01L2224/06177 ,  H01L2224/08148 ,  H01L2224/11462 ,  H01L2224/13023 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/14131 ,  H01L2224/14136 ,  H01L2224/16145 ,  H01L2224/26145 ,  H01L2224/26175 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49176 ,  H01L2224/73204 ,  H01L2224/73207 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/80903 ,  H01L2224/81193 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: A semiconductor device includes: on an upper surface of a second semiconductor chip on a circuit board, a ring dam section formed at an outer circumference of a mounting region above which a first semiconductor chip is mounted; and an interconnect extending from the dam section to a center section of the first semiconductor chip or the second semiconductor chip in a region in which the first semiconductor chip faces the second semiconductor chip. The interconnect is electrically connected to a connection terminal on a circuit formation surface of the first or second semiconductor chip at the center section of the first or second semiconductor chip. The dam section and the interconnect are power supply interconnects or ground interconnects.

Abstract translation: 一种半导体器件，包括：在电路板上的第二半导体芯片的上表面上，形成在安装区域的外周上的环形阻挡部分，在其上安装有第一半导体芯片; 以及在第一半导体芯片面向第二半导体芯片的区域中从堤坝部分延伸到第一半导体芯片或第二半导体芯片的中心部分的互连。 互连电连接到第一或第二半导体芯片的中心部分处的第一或第二半导体芯片的电路形成表面上的连接端子。 坝段和互连是电源互连或接地互连。

公开(公告)号：US20140217579A1

公开(公告)日：2014-08-07

申请号：US13977658

申请日：2011-12-31

Applicant: Sanka Ganesan ,  Zhiguo Qian ,  Robert L. Sankman ,  Krishna Srinivasan ,  Zhaohui Zhu

Inventor： Sanka Ganesan ,  Zhiguo Qian ,  Robert L. Sankman ,  Krishna Srinivasan ,  Zhaohui Zhu

IPC: H01L23/498 ,  H01L21/768

CPC classification number: H01L23/49811 ,  H01L21/76885 ,  H01L23/50 ,  H01L23/5386 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/10126 ,  H01L2224/1147 ,  H01L2224/1182 ,  H01L2224/11831 ,  H01L2224/11849 ,  H01L2224/1301 ,  H01L2224/13013 ,  H01L2224/13014 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13562 ,  H01L2224/1357 ,  H01L2224/13687 ,  H01L2224/14132 ,  H01L2224/14133 ,  H01L2224/14135 ,  H01L2224/14136 ,  H01L2224/16013 ,  H01L2224/16014 ,  H01L2224/16058 ,  H01L2224/16238 ,  H01L2224/1703 ,  H01L2224/17051 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81385 ,  H01L2224/81395 ,  H01L2224/81411 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81815 ,  H01L2924/05042 ,  H01L2924/1434 ,  H01L2924/381 ,  H01L2924/3841 ,  H01L2924/014 ,  H01L2924/00014

Abstract: Electronic assemblies and methods including the formation of interconnect structures are described. In one embodiment an apparatus includes semiconductor die and a first metal bump on the die, the first metal bump including a surface having a first part and a second part. The apparatus also includes a solder resistant coating covering the first part of the surface and leaving the second part of the surface uncovered. Other embodiments are described and claimed.

Abstract translation: 描述了包括形成互连结构的电子组件和方法。 在一个实施例中，一种装置包括半导体管芯和裸片上的第一金属凸块，第一金属凸块包括具有第一部分和第二部分的表面。 该设备还包括覆盖表面的第一部分并且使表面的第二部分未被覆盖的耐焊接涂层。 描述和要求保护其他实施例。

公开(公告)号：US20140145331A1

公开(公告)日：2014-05-29

申请号：US14056839

申请日：2013-10-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： DOO-HEE HWANG ,  SANG-KIL LEE

IPC: H01L23/498

CPC classification number: H01L25/0652 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/06135 ,  H01L2224/06136 ,  H01L2224/06181 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/14136 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2224/05552

Abstract: A multi-chip package may include a system on a chip (SOC) and a plurality of memory devices arranged in the same layer on the SOC. Accordingly, as the multi-chip package may not need to use a TSV, so that manufacturing cost of the multi-chip package is reduced. Moreover, a memory bandwidth between the SOC and the first and second memory devices may increase.

Abstract translation: 多芯片封装可以包括芯片上的系统（SOC）和布置在SOC上的同一层中的多个存储器件。 因此，由于多芯片封装可能不需要使用TSV，所以降低了多芯片封装的制造成本。 此外，SOC和第一和第二存储器件之间的存储器带宽可能增加。