公开(公告)号：US20240128138A1

公开(公告)日：2024-04-18

申请号：US18392368

申请日：2023-12-21

申请人： Intel Corporation

发明人： Robert L. Sankman ,  Rahul N. Manepalli ,  Robert Alan May ,  Srinivas Venkata Ramanuja Pietambaram ,  Bharat P. Penmecha

IPC分类号： H01L23/15 ,  H01L21/48 ,  H01L23/31 ,  H01L23/538 ,  H01L25/065

CPC分类号： H01L23/15 ,  H01L21/486 ,  H01L23/3128 ,  H01L23/5381 ,  H01L23/5384 ,  H01L25/0655

摘要： Semiconductor packages and methods for forming semiconductor packages are disclosed. An example semiconductor package includes a substrate and a core. An insulator material is present over the core, and along a direction perpendicular to a first surface of the core, a portion of the insulator material is between the core and a first surface of the substrate. A via extends between the first surface of the core and a second surface of the core in the direction perpendicular to the first surface of the core. A bridge die is in a recess in the substrate. The bridge die is coupled with the via. An electronic component is coupled to an end of the via at a second surface of the substrate.

公开(公告)号：US11444033B2

公开(公告)日：2022-09-13

申请号：US16918900

申请日：2020-07-01

申请人： Intel Corporation

发明人： Robert Starkston ,  Robert L. Sankman ,  Scott M. Mokler ,  Richard C. Stamey

IPC分类号： H01L23/538 ,  H01L21/683 ,  H01L21/48 ,  H01L23/498 ,  H01L25/065

摘要： A hybrid microelectronic substrate may be formed by the incorporation of a high density microelectronic patch substrate within a lower density microelectronic substrate. The hybrid microelectronic substrate may allow for direct flip chip attachment of a microelectronic device having high density interconnections to the high density microelectronic patch substrate portion of the hybrid microelectronic substrate, while allowing for lower density interconnection and electrical routes in areas where high density interconnections are not required.

公开(公告)号：US11410919B2

公开(公告)日：2022-08-09

申请号：US16645744

申请日：2017-12-30

申请人： Intel Corporation

发明人： Robert L. Sankman ,  Sanka Ganesan

IPC分类号： H01L23/498 ,  H01L21/48 ,  H01L23/31 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00

摘要： Embodiments include semiconductor packages and a method of forming the semiconductor packages. A semiconductor package includes a base die disposed on an interposer. The semiconductor package also has a plurality of dies on top of one another to form a stack on the base die. Each die has a top surface and a bottom surface that is opposite from the top surface, and each die has one or more die contacts on at least one of the top surface and the bottom surface that are each electrically coupled to at least one die contact of the base die with one or more wire bonds. The semiconductor package includes a mold layer disposed over and around the plurality of dies, the base die, and the one or more wire bonds. The base die may have a first surface area that exceeds a second surface area of the plurality of stacked dies.

公开(公告)号：US11276630B2

公开(公告)日：2022-03-15

申请号：US16842954

申请日：2020-04-08

申请人： Intel Corporation

发明人： Robert L. Sankman ,  Sanka Ganesan

IPC分类号： H01L23/00 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31

摘要： Generally discussed herein are systems, methods, and apparatuses that include conductive pillars that are about co-planar. According to an example, a technique can include growing conductive pillars on respective exposed landing pads of a substrate, situating molding material around and on the grown conductive pillars, removing, simultaneously, a portion of the grown conductive pillars and the molding material to make the grown conductive pillars and the molding material about planar, and electrically coupling a die to the conductive pillars.

公开(公告)号：US11257804B2

公开(公告)日：2022-02-22

申请号：US16902123

申请日：2020-06-15

申请人： INTEL CORPORATION

发明人： Wilfred Gomes ,  Mark T. Bohr ,  Rajesh Kumar ,  Robert L. Sankman ,  Ravindranath V. Mahajan ,  Wesley D. Mc Cullough

IPC分类号： H01L25/18 ,  H01L23/48 ,  H01L25/00 ,  H01L23/00 ,  H01L23/538 ,  H01L23/522 ,  H01L25/16 ,  H01L25/065 ,  H01L23/498

摘要： The present disclosure is directed to systems and methods of conductively coupling a plurality of relatively physically small core dies to a relatively physically larger base die using an electrical mesh network that is formed in whole or in part in, on, across, or about all or a portion of the base die. Electrical mesh networks beneficially permit the positioning of the cores in close proximity to support circuitry carried by the base die. The minimal separation between the core circuitry and the support circuitry advantageously improves communication bandwidth while reducing power consumption. Each of the cores may include functionally dedicated circuitry such as processor core circuitry, field programmable logic, memory, or graphics processing circuitry. The use of core dies beneficially and advantageously permits the use of a wide variety of cores, each having a common or similar interface to the electrical mesh network.

公开(公告)号：US11222877B2

公开(公告)日：2022-01-11

申请号：US15721235

申请日：2017-09-29

申请人： Intel Corporation

发明人： Omkar Karhade ,  Robert L. Sankman ,  Nitin A. Deshpande ,  Mitul Modi ,  Thomas J. De Bonis ,  Robert M. Nickerson ,  Zhimin Wan ,  Haifa Hariri ,  Sri Chaitra J. Chavali ,  Nazmiye Acikgoz Akbay ,  Fadi Y. Hafez ,  Christopher L. Rumer

IPC分类号： H01L25/10 ,  H01L23/367 ,  H01L25/00 ,  H01L23/373 ,  H01L23/42 ,  H01L23/498

摘要： The present disclosure is directed to systems and methods for improving heat distribution and heat removal efficiency in PoP semiconductor packages. A PoP semiconductor package includes a first semiconductor package that is physically, communicably, and conductively coupled to a stacked second semiconductor package. A thermally conductive member that includes at least one thermally conductive member may be disposed between the first semiconductor package and the second semiconductor package. The thermally conductive member may include: a single thermally conductive element; multiple thermally conductive elements; or a core that includes at least one thermally conductive element. The thermally conductive elements are thermally conductively coupled to an upper surface of the first semiconductor package and to the lower surface of the second semiconductor package to facilitate the transfer of heat from the first semiconductor package to the second semiconductor package.

公开(公告)号：US20210193579A1

公开(公告)日：2021-06-24

申请号：US16724907

申请日：2019-12-23

申请人： Intel Corporation

发明人： Sanka Ganesan ,  Robert L. Sankman ,  Sri Chaitra Jyotsna Chavali

IPC分类号： H01L23/538 ,  H01L23/498 ,  H01L21/768

摘要： Various examples provide a semiconductor package. The semiconductor package includes a substrate having first and second opposed substantially planar major surfaces extending in an x-y direction. The package further includes a bridge die having third and fourth opposed substantially planar major surfaces extending in the x-y direction. The third substantially planar major surface of the bridge die is in direct contact with the second substantially planar major surface of the substrate. The semiconductor package further includes a through silicon via extending in a z-direction through the first substantially planar major surface of the substrate and the fourth substantially planar major surface of the bridge die. The semiconductor package further includes a power source coupled to the through silicon via, a first electronic component electronically coupled to the bridge die, and a second electronic component electronically coupled to the bridge die. The semiconductor package further includes an overmold at least partially encasing the first electronic component, second electronic component, and the bridge die.

公开(公告)号：US10811366B2

公开(公告)日：2020-10-20

申请号：US16249457

申请日：2019-01-16

申请人： Intel Corporation

发明人： Feras Eid ,  Robert L. Sankman ,  Sandeep B. Sane

IPC分类号： H01L23/49 ,  H01L21/48 ,  H01L23/00 ,  H01L23/498

摘要： A microelectronic package may be fabricated with at least one compliant external bond pad having at least one integrated spring structure for mitigating the effects of warpage of the microelectronic package during attachment to an external substrate. An embodiment for the microelectronic package may include a microelectronic package substrate having a first surface and an opposing second surface, wherein the microelectronic package substrate includes a void defined therein that extends into the microelectronic package substrate from the second surface thereof, and a compliant bond pad suspended over the void, wherein the compliant bond pad includes a land portion and at least one spring portion, and wherein the at least one spring portion extends from the compliant bond pad land portion to an anchor structure on the microelectronic package substrate second surface.

公开(公告)号：US10535595B2

公开(公告)日：2020-01-14

申请号：US15776402

申请日：2015-12-26

申请人： Intel Corporation

发明人： Robert L. Sankman ,  Adel A. Elsherbini

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L23/498 ,  H01L25/065 ,  H01L23/538 ,  H01L23/00

摘要： Embodiments are generally directed to a conductive base embedded interconnect. An embodiment of an apparatus includes a substrate; an embedded interconnect layer in a first side of the substrate, the embedded interconnect layer including a plurality of contacts; and one or more conductive paths through the substrate, the one or more conductive paths being connected with the embedded interconnect layers.

公开(公告)号：US20190371778A1

公开(公告)日：2019-12-05

申请号：US15996870

申请日：2018-06-04

申请人： Intel Corporation

发明人： Robert L. Sankman ,  Sairam Agraharam ,  Shengquan Ou ,  Thomas J. De Bonis ,  Todd Spencer ,  Yang Sun ,  Guotao Wang

IPC分类号： H01L25/00 ,  H01L21/56 ,  H01L23/538 ,  H01L25/18 ,  H01L23/00

摘要： An electronic device may include a first die that may include a first set of die contacts. The electronic device may include a second die that may include a second set of die contacts. The electronic device may include a bridge interconnect that may include a first set of bridge contacts and may include a second set of bridge contacts. The first set of bridge contacts may be directly coupled to the first set of die contacts (e.g., with an interconnecting material, such as solder). The second set of bridge contacts may be directly coupled to the second set of die contacts (e.g., with solder). The bridge interconnect may help facilitate electrical communication between the first die and the second die.