公开(公告)号：US12148744B2

公开(公告)日：2024-11-19

申请号：US17132976

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Zhichao Zhang ,  Kemal Aygün ,  Suresh V. Pothukuchi ,  Xiaoqian Li ,  Omkar Karhade

IPC: H04B10/00 ,  G02B6/42 ,  H01L25/00 ,  H01L25/18 ,  H01L23/373 ,  H01L23/538

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques related to disaggregating co-packaged SOC and photonic integrated circuits on an multichip package. The photonic integrated circuits may also be silicon photonics engines. In embodiments, multiple SOCs and photonic integrated circuits may be electrically coupled, respectively, into modules, with multiple modules then incorporated into an MCP using a stacked die structure. Other embodiments may be described and/or claimed.

公开(公告)号：US20240063180A1

公开(公告)日：2024-02-22

申请号：US17891654

申请日：2022-08-19

Applicant: Intel Corporation

Inventor： Kimin Jun ,  Adel Elsherbini ,  Omkar Karhade ,  Bhaskar Jyoti Krishnatreya ,  Mohammad Enamul Kabir ,  Jiraporn Seangatith ,  Tushar Talukdar ,  Shawna Liff ,  Johanna Swan ,  Feras Eid

IPC: H01L25/065 ,  H01L25/00 ,  H01L21/48 ,  H01L23/13 ,  H01L23/31

CPC classification number: H01L25/0652 ,  H01L25/50 ,  H01L21/4857 ,  H01L23/13 ,  H01L23/3185 ,  H01L24/05

Abstract: Quasi-monolithic multi-die composites including a primary fill structure within a space between adjacent IC dies. A fill material layer, which may have inorganic composition, may be bonded to a host substrate and patterned to form a primary fill structure that occupies a first portion of the host substrate. IC dies may be bonded to regions of the host substrate within openings where the primary fill structure is absent to have a spatial arrangement complementary to the primary fill structure. The primary fill structure may have a thickness substantially matching that of IC dies and/or be co-planar with a surface of one or more of the IC dies. A gap fill material may then be deposited within remnants of the openings to form a secondary fill structure that occupies space between the IC dies and the primary fill structure.

公开(公告)号：US20230207525A1

公开(公告)日：2023-06-29

申请号：US17561845

申请日：2021-12-24

Applicant: Intel Corporation

Inventor： Debendra Mallik ,  Sriram Srinivasan ,  Christopher Pelto ,  Gwang-Soo Kim ,  Nitin Deshpande ,  Omkar Karhade

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L25/0657 ,  H01L23/3185 ,  H01L24/08 ,  H01L24/16 ,  H01L24/73 ,  H01L2224/08145 ,  H01L2224/16145 ,  H01L2224/73253 ,  H01L2225/06568

Abstract: A packaged device comprises first die stack and a third die. The first die stack includes a first die comprising first conductive contacts each at a first side of the first die, and a second die comprising second conductive contacts each at a second side of the second die. First solder bonds which each extend to a respective one of the first conductive contacts. The third die comprises third conductive contacts each at a third side of the third die. The third die is coupled to the first die stack via second solder bonds which each extend to a respective one of the second conductive contacts, and to a respective one of the third conductive contacts. Each die of the first die stack is coupled to each of a respective one or more other dies of the first die stack via respective hybrid bonds.

公开(公告)号：US20230197685A1

公开(公告)日：2023-06-22

申请号：US17558995

申请日：2021-12-22

Applicant: Intel Corporation

Inventor： Omkar Karhade ,  Sairam Agraharam

IPC: H01L25/065 ,  H01L23/00 ,  H01L21/78

CPC classification number: H01L25/0657 ,  H01L24/08 ,  H01L24/80 ,  H01L21/78 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896

Abstract: Microelectronic stacked die package structures formed according to some embodiments may include a first die comprising a first conductive layer over a substrate layer. A second die may be on the first conductive layer. A third die is on the second die. An edge region of the stacked die package structure comprises a first portion over a second portion, the first portion comprising edges of the third die, the second die, and the first conductive layer, and the second portion comprising the substrate layer of the first die, wherein the first portion comprises a curved profile, and the second portion comprises a substantially vertical profile.

公开(公告)号：US20220102242A1

公开(公告)日：2022-03-31

申请号：US17032577

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Mitul Modi ,  Joseph Van Nausdle ,  Omkar Karhade ,  Edvin Cetegen ,  Nicholas Haehn ,  Vaibhav Agrawal ,  Digvijay Raorane ,  Dingying Xu ,  Ziyin Lin ,  Yiqun Bai

IPC: H01L23/42 ,  H01L23/31 ,  H01L21/48

Abstract: Techniques and mechanisms for facilitating heat conductivity in a packaged device with a dummy die. In an embodiment, a packaged device comprises a substrate and one or more IC die coupled to a surface thereof. A dummy die, adjacent to an IC die and coupled to a region of the substrate, comprises a polymer resin and a filler. A package mold structure of the packaged device adjoins respective sides of the IC die and the dummy die, and adjoins the surface of the substrate. In another embodiment, a first CTE of the dummy die is less than a second CTE of the package mold structure, and a first thermal conductivity of the dummy die is greater than a second thermal conductivity of the package mold structure.

公开(公告)号：US20200273768A1

公开(公告)日：2020-08-27

申请号：US16287668

申请日：2019-02-27

Applicant: Intel Corporation

Inventor： Omkar Karhade ,  Nitin Deshpande ,  Mitul Modi ,  Edvin Cetegen ,  Aastha Uppal ,  Debendra Mallik ,  Sanka Ganesan ,  Yiqun Bai ,  Jan Krajniak ,  Kumar Singh

IPC: H01L23/31 ,  H01L23/532 ,  H01L23/34 ,  H01L23/00 ,  H01L21/56

Abstract: IC packages including a heat spreading material comprising crystalline carbon. The heat spreading material may be applied directly to an IC die surface, for example at a die prep stage, prior to an application or build-up of packaging material, so that the high thermal conductivity may best mitigate any hot spots that develop at the IC die surface during operation. The heat spreading material may be applied to surface of the IC die.

公开(公告)号：US20190104610A1

公开(公告)日：2019-04-04

申请号：US15720488

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Robert Nickerson ,  Nitin Deshpande ,  Omkar Karhade ,  Thomas De Bonis

IPC: H05K1/02 ,  H05K1/14 ,  H05K3/00

Abstract: Methods/structures of joining package structures are described. Those methods/structures may include a first substrate comprising a first die, wherein an underfill material is disposed on a first surface of the first substrate adjacent the first die; and a second substrate disposed on the first substrate, wherein the second substrate comprises at least one opening disposed over the first die, wherein the at least one opening is at least partially filled with the underfill material.

公开(公告)号：US09991243B2

公开(公告)日：2018-06-05

申请号：US15437237

申请日：2017-02-20

Applicant: Intel Corporation

Inventor： Omkar Karhade ,  Nitin Deshpande ,  Bassam M. Ziadeh ,  Yoshihiro Tomita

IPC: H01L23/48 ,  H01L25/18 ,  H01L25/065 ,  H01L23/538 ,  H01L23/498 ,  H01L25/00 ,  H01L23/00 ,  H01L25/16

CPC classification number: H01L25/18 ,  H01L23/481 ,  H01L23/49838 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/16 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/26155 ,  H01L2224/26175 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/49109 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81 ,  H01L2224/81203 ,  H01L2224/83 ,  H01L2224/83851 ,  H01L2224/85 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06558 ,  H01L2225/06593 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15153 ,  H01L2924/19104 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2224/45099

Abstract: An integrated circuit assembly that includes a substrate; a member formed on the substrate; a first die mounted to the substrate within an opening in the member such that there is space between the first die and the member and the member surrounds the first die, and wherein the first die does not extend above an upper surface of the member; an underfill between the first the die and the substrate, wherein the underfill at least partially fills the space between the die and member; and a second die mounted to the first die and the member, wherein the second die is mounted to the member on all sides of the opening.

公开(公告)号：US09795038B2

公开(公告)日：2017-10-17

申请号：US14496560

申请日：2014-09-25

Applicant: Intel Corporation

Inventor： Omkar Karhade ,  Nitin Deshpande ,  Nachiket Raravikar

IPC: H01L23/34 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H05K3/30 ,  H01L23/00

CPC classification number: H05K3/305 ,  H01L23/562 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/3511 ,  H05K2201/10734 ,  H05K2203/0191 ,  Y02P70/613 ,  H01L2924/00

Abstract: Some example forms relate to an electronic package. The electronic package includes an electronic component and a substrate that includes a front side and a back side. The electronic component is mounted on the front side of the substrate and conductors are mounted on the back side of the substrate. The substrate is warped due to differences in the coefficients of thermal expansion between the electronic component and the substrate. An adhesive is positioned between the conductors on the back side of the substrate and an adhesive film is attached to the adhesive positioned between the conductors on the back side of the substrate.

公开(公告)号：US20170170087A1

公开(公告)日：2017-06-15

申请号：US14967993

申请日：2015-12-14

Applicant: Intel Corporation

Inventor： Omkar Karhade ,  Kedar Dhane

IPC: H01L23/16

CPC classification number: H01L23/16 ,  H01L23/562 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/92 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/3511 ,  H01L2924/3512

Abstract: An electronic package that includes a substrate; a die attached to the substrate; an underfill positioned between the die and the substrate due to capillary action; a first support adjacent to the die and attached to the substrate; and a second support mounted on the first support, wherein the second support is closer to the die than the first support, wherein first support surrounds the die and the second support surrounds the die, and wherein the second support is a different material than the first support. The die may be flip chip bonded to the substrate and the underfill may secure the die to the substrate. The first support may be attached to the substrate using an adhesive and the second support may be attached to the first support using an adhesive.