公开(公告)号：US11664294B2

公开(公告)日：2023-05-30

申请号：US16241158

申请日：2019-01-07

Applicant: INTEL CORPORATION

Inventor： Aastha Uppal ,  Je-Young Chang ,  Weihua Tang ,  Minseok Ha

IPC: H01L21/56 ,  H01L23/34 ,  H01L23/427 ,  H01L23/00 ,  H01L23/552 ,  H01L23/31 ,  H01L21/48

CPC classification number: H01L23/427 ,  H01L21/4882 ,  H01L21/565 ,  H01L23/3128 ,  H01L23/552 ,  H01L24/09 ,  H01L24/17 ,  H01L24/73 ,  H01L24/81 ,  H01L2924/14

Abstract: An integrated circuit assembly may be formed using a phase change material as an electromagnetic shield and as a heat dissipation mechanism for the integrated circuit assembly. In one embodiment, the integrated circuit assembly may comprise an integrated circuit package including a first substrate having a first surface and an opposing second surface, and at least one integrated circuit device having a first surface and an opposing second surface, wherein the at least one integrated circuit device is electrically attached by the first surface thereof to the first surface of the first substrate; and a phase change material formed on the integrated circuit package.

公开(公告)号：US20210235596A1

公开(公告)日：2021-07-29

申请号：US16750217

申请日：2020-01-23

Applicant: Intel Corporation

Inventor： Aastha Uppal ,  Je-Young Chang ,  Ravindranath Mahajan

IPC: H05K7/20

Abstract: An integrated circuit assembly may be formed comprising an electronic substrate, at least one integrated circuit device electrically attached to the electronic substrate, a heat dissipation device comprising a main body portion and a resilient portion extending from the main body portion, wherein the resilient portion has a plurality of extensions, a thermal interface material between the at least one integrated circuit device and the heat dissipation device, and a stiffener attached to the electronic substrate, wherein at least a portion of the plurality of extensions of the resilient portion of the heat dissipation device are biased against the stiffener.

公开(公告)号：US20200273768A1

公开(公告)日：2020-08-27

申请号：US16287668

申请日：2019-02-27

Applicant: Intel Corporation

Inventor： Omkar Karhade ,  Nitin Deshpande ,  Mitul Modi ,  Edvin Cetegen ,  Aastha Uppal ,  Debendra Mallik ,  Sanka Ganesan ,  Yiqun Bai ,  Jan Krajniak ,  Kumar Singh

IPC: H01L23/31 ,  H01L23/532 ,  H01L23/34 ,  H01L23/00 ,  H01L21/56

Abstract: IC packages including a heat spreading material comprising crystalline carbon. The heat spreading material may be applied directly to an IC die surface, for example at a die prep stage, prior to an application or build-up of packaging material, so that the high thermal conductivity may best mitigate any hot spots that develop at the IC die surface during operation. The heat spreading material may be applied to surface of the IC die.

公开(公告)号：US12048123B2

公开(公告)日：2024-07-23

申请号：US16750217

申请日：2020-01-23

Applicant: Intel Corporation

Inventor： Aastha Uppal ,  Je-Young Chang ,  Ravindranath Mahajan

IPC: H05K7/20

CPC classification number: H05K7/205

Abstract: An integrated circuit assembly may be formed comprising an electronic substrate, at least one integrated circuit device electrically attached to the electronic substrate, a heat dissipation device comprising a main body portion and a resilient portion extending from the main body portion, wherein the resilient portion has a plurality of extensions, a thermal interface material between the at least one integrated circuit device and the heat dissipation device, and a stiffener attached to the electronic substrate, wherein at least a portion of the plurality of extensions of the resilient portion of the heat dissipation device are biased against the stiffener.

公开(公告)号：US11574851B2

公开(公告)日：2023-02-07

申请号：US16287116

申请日：2019-02-27

Applicant: Intel Corporation

Inventor： Aastha Uppal ,  Omkar Karhade ,  Ram Viswanath ,  Je-Young Chang ,  Weihua Tang ,  Nitin Deshpande ,  Mitul Modi ,  Edvin Cetegen ,  Sanka Ganesan ,  Yiqun Bai ,  Jan Krajniak ,  Kumar Singh

IPC: H01L23/00 ,  H01L23/367 ,  H01L23/373 ,  H01L23/427 ,  H01L25/18 ,  H01L21/56

Abstract: An apparatus is provided which comprises: a package substrate, an integrated circuit device coupled to a surface of the package substrate, a first material on the surface of the package substrate, the first material contacting one or more lateral sides of the integrated circuit device, the first material extending at least to a surface of the integrated circuit device opposite the package substrate, two or more separate fins over a surface of the integrated circuit device, the two or more fins comprising a second material having a different composition than the first material, and a third material having a different composition than the second material, the third material over the surface of the integrated circuit device and between the two or more fins. Other embodiments are also disclosed and claimed.

公开(公告)号：US11545407B2

公开(公告)日：2023-01-03

申请号：US16244748

申请日：2019-01-10

Applicant: Intel Corporation

Inventor： Kumar Abhishek Singh ,  Omkar Karhade ,  Nitin Deshpande ,  Mitul Modi ,  Edvin Cetegen ,  Aastha Uppal ,  Debendra Mallik ,  Sanka Ganesan ,  Yiqun Bai ,  Jan Krajniak ,  Manish Dubey ,  Ravindranath Mahajan ,  Ram Viswanath ,  James C. Matayabas, Jr.

IPC: H01L23/10 ,  H01L23/34 ,  H01L23/31 ,  H01L23/00 ,  H01L23/48 ,  H01L21/56 ,  H01L21/48

Abstract: An integrated circuit package may be formed having at least one heat dissipation structure within the integrated circuit package itself. In one embodiment, the integrated circuit package may include a substrate; at least one integrated circuit device, wherein the at least one integrated circuit device is electrically attached to the substrate; a mold material on the substrate and adjacent to the at least one integrated circuit device; and at least one heat dissipation structure contacting the at least one integrated circuit, wherein the at least one heat dissipation structure is embedded either within the mold material or between the mold material and the substrate.

公开(公告)号：US20200294884A1

公开(公告)日：2020-09-17

申请号：US16355596

申请日：2019-03-15

Applicant: Intel Corporation

Inventor： Javed Shaikh ,  Je-Young Chang ,  Kelly Lofgreen ,  Weihua Tang ,  Aastha Uppal

IPC: H01L23/38 ,  H01L35/10 ,  H01L35/16 ,  H01L35/18 ,  H01L35/30

Abstract: An Integrated Circuit (IC) assembly, comprising an IC package coupled to a substrate, and a subassembly comprising a thermal interface layer. The thermal interface layer comprises a phase change material (PCM) over the IC package. At least one thermoelectric cooling (TEC) apparatus is thermally coupled to the thermal interface layer.

公开(公告)号：US10600699B2

公开(公告)日：2020-03-24

申请号：US15685772

申请日：2017-08-24

Applicant: Intel Corporation

Inventor： Aastha Uppal ,  Je-Young Chang ,  Shankar Devasenathipathy ,  Joseph B. Petrini

IPC: H01L21/66 ,  G01K7/22 ,  H01L23/498 ,  G01K1/02 ,  G01K1/14 ,  H01L23/427

Abstract: Embodiments of the present disclosure provide techniques and configurations for inspection of a package assembly with a thermal solution, in accordance with some embodiments. In embodiments, an apparatus for inspection of a package assembly with a thermal solution may include a first fixture to house the package assembly on the apparatus, and a second fixture to house at least a portion of a thermal solution that is to be disposed on top of the package assembly. The apparatus may further include a load actuator, to apply a load to a die of the package assembly, via the thermal solution, and a plurality of sensors disposed around the thermal solution and the package assembly, to perform in situ thermal and/or mechanical measurements associated with the application of the load to the die of the package assembly. Other embodiments may be described and/or claimed.

公开(公告)号：US12021016B2

公开(公告)日：2024-06-25

申请号：US16898196

申请日：2020-06-10

Applicant: Intel Corporation

Inventor： Chandra Mohan Jha ,  Pooya Tadayon ,  Aastha Uppal ,  Weihua Tang ,  Paul Diglio ,  Xavier Brun

IPC: H01L23/498 ,  H01L21/56 ,  H01L21/78 ,  H01L23/373 ,  H01L23/522

CPC classification number: H01L23/49833 ,  H01L21/561 ,  H01L21/78 ,  H01L23/3732 ,  H01L23/3738 ,  H01L23/5226

Abstract: Embodiments disclosed herein comprise a die and methods of forming a die. In an embodiment, a die comprises, a die substrate, wherein the die substrate has a first thermal conductivity, and a first layer over the die substrate, wherein the first layer has a second thermal conductivity that is greater than the first thermal conductivity. In an embodiment, the die further comprises a second layer over the first layer, wherein the second layer comprises transistors.

公开(公告)号：US11769753B2

公开(公告)日：2023-09-26

申请号：US16051065

申请日：2018-07-31

Applicant: Intel Corporation

Inventor： George Vakanas ,  Aastha Uppal ,  Shereen Elhalawaty ,  Aaron McCann ,  Edvin Cetegen ,  Tannaz Harirchian ,  Saikumar Jayaraman

IPC: H01L25/065 ,  H01L23/373 ,  H01L23/367 ,  H01L23/00 ,  H10B12/00

CPC classification number: H01L25/0657 ,  H01L23/367 ,  H01L23/3736 ,  H01L24/49 ,  H10B12/00

Abstract: Embodiments disclosed herein include an electronics package and methods of forming such electronics packages. In an embodiment, the electronics package comprises a package substrate, and a first die coupled to the package substrate. In an embodiment, a cavity is formed through the package substrate. In an embodiment, the cavity is within a footprint of the first die. In an embodiment, the electronics package further comprises a thermal stack in the cavity. In an embodiment, the thermal stack contacts the first die.