公开(公告)号：US12051647B2

公开(公告)日：2024-07-30

申请号：US18199735

申请日：2023-05-19

Applicant: Intel Corporation

Inventor： Andrew Collins ,  Bharat P. Penmecha ,  Rajasekaran Swaminathan ,  Ram Viswanath

IPC: H01L23/528 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H01L25/18

CPC classification number: H01L23/5283 ,  H01L23/49838 ,  H01L23/5381 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5385 ,  H01L24/17 ,  H01L24/23 ,  H01L25/0655 ,  H01L25/18

Abstract: Various embodiments relate to a semiconductor package. The semiconductor package includes a first die. The first die includes a first bridge interconnect region. The semiconductor package further includes a second die. The second die includes a second bridge interconnect region. The semiconductor package includes a bridge die. The bridge die includes a first contact area to connect to the first bridge interconnect region and a second contact area to connect to the second bridge interconnect region. In the semiconductor package, the first bridge interconnect region is larger than the second bridge interconnect region. Additionally, each of the first bridge interconnect region and the second bridge interconnect region include a plurality of conductive bumps. An average pitch between adjacent bumps of the first bridge interconnect region is larger than an average pitch between adjacent bumps of the second bridge interconnect region.

公开(公告)号：US20240136244A1

公开(公告)日：2024-04-25

申请号：US18395351

申请日：2023-12-22

Applicant: Intel Corporation

Inventor： Debendra Mallik ,  Je-Young Chang ,  Ram Viswanath ,  Elah Bozorg-Grayeli ,  Ahmad Al Mohammad

IPC: H01L23/367 ,  H01L23/373 ,  H01L23/495

CPC classification number: H01L23/3672 ,  H01L23/373 ,  H01L23/49568

Abstract: Thermal heat spreaders and/or an IC die with solderable thermal structures may be assembled together with a solder array thermal interconnects. A thermal heat spreader may include a non-metallic material and one or more metallized surfaces suitable for bonding to a solder alloy employed as thermal interface material between the heat spreader and an IC die. An IC die may include a metallized back-side surface similarly suitable for bonding to a thermal interconnect comprising a solder alloy. Metallization on the IC die and/or heat spreader may comprise a plurality of solderable structures. A multi-chip package may include multiple IC die having different die thickness that are accommodated by a z-height thickness variation in the thermal interconnects and/or the solderable structures of the IC die or heat spreader.

公开(公告)号：US11705398B2

公开(公告)日：2023-07-18

申请号：US17585082

申请日：2022-01-26

Applicant: Intel Corporation

Inventor： Andrew Collins ,  Bharat P. Penmecha ,  Rajasekaran Swaminathan ,  Ram Viswanath

IPC: H01L23/538 ,  H01L23/528 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: H01L23/5283 ,  H01L23/49838 ,  H01L23/5381 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5385 ,  H01L24/17 ,  H01L24/23 ,  H01L25/0655 ,  H01L25/18

Abstract: Various embodiments relate to a semiconductor package. The semiconductor package includes a first die. The first die includes a first bridge interconnect region. The semiconductor package further includes a second die. The second die includes a second bridge interconnect region. The semiconductor package includes a bridge die. The bridge die includes a first contact area to connect to the first bridge interconnect region and a second contact area to connect to the second bridge interconnect region. In the semiconductor package, the first bridge interconnect region is larger than the second bridge interconnect region. Additionally, each of the first bridge interconnect region and the second bridge interconnect region include a plurality of conductive bumps. An average pitch between adjacent bumps of the first bridge interconnect region is larger than an average pitch between adjacent bumps of the second bridge interconnect region.

公开(公告)号：US20230134770A1

公开(公告)日：2023-05-04

申请号：US18090795

申请日：2022-12-29

Applicant: Intel Corporation

Inventor： Sanka Ganesan ,  Ram Viswanath ,  Xavier Francois Brun ,  Tarek A. Ibrahim ,  Jason M. Gamba ,  Manish Dubey ,  Robert Alan May

IPC: H01L23/538 ,  H01L23/367 ,  H01L23/31 ,  H01L23/00

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic component may include a substrate having a first face and an opposing second face, wherein the substrate includes a through-substrate via (TSV); a first mold material region at the first face, wherein the first mold material region includes a first through-mold via (TMV) conductively coupled to the TSV; and a second mold material region at the second face, wherein the second mold material region includes a second TMV conductively coupled to the TSV.

公开(公告)号：US11640942B2

公开(公告)日：2023-05-02

申请号：US17677130

申请日：2022-02-22

Applicant: Intel Corporation

Inventor： Sanka Ganesan ,  Ram Viswanath ,  Xavier Francois Brun ,  Tarek A. Ibrahim ,  Jason M. Gamba ,  Manish Dubey ,  Robert Alan May

IPC: H01L23/538 ,  H01L23/367 ,  H01L23/31 ,  H01L23/00

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic component may include a substrate having a first face and an opposing second face, wherein the substrate includes a through-substrate via (TSV); a first mold material region at the first face, wherein the first mold material region includes a first through-mold via (TMV) conductively coupled to the TSV; and a second mold material region at the second face, wherein the second mold material region includes a second TMV conductively coupled to the TSV.

公开(公告)号：US20250006643A1

公开(公告)日：2025-01-02

申请号：US18217049

申请日：2023-06-30

Applicant: Intel Corporation

Inventor： Debendra Mallik ,  Ram Viswanath ,  Xavier Brun

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/00 ,  H01L23/373 ,  H01L23/498 ,  H01L25/065

Abstract: Microelectronic integrated circuit package structures include a package substrate with a first die over the package substrate, and a second die adjacent to the first die, such that first sides of the first die and the second die are on a thermal solution. A bridge structure is directly on a portion of each of second sides of the first and second dies, such that the second sides include integrated circuit contact structures. Bridge via structures couple the integrated circuit contact structures to the bridge structure.

公开(公告)号：US11984377B2

公开(公告)日：2024-05-14

申请号：US16831068

申请日：2020-03-26

Applicant: Intel Corporation

Inventor： Debendra Mallik ,  Je-Young Chang ,  Ram Viswanath ,  Elah Bozorg-Grayeli ,  Ahmad Al Mohammad

IPC: H01L23/367 ,  H01L21/48 ,  H01L23/00 ,  H01L23/18 ,  H01L23/373 ,  H01L23/538

CPC classification number: H01L23/3675 ,  H01L21/4875 ,  H01L23/18 ,  H01L23/3735 ,  H01L23/5383 ,  H01L23/5386 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/33 ,  H01L24/73 ,  H01L2224/16227 ,  H01L2224/16245 ,  H01L2224/17181 ,  H01L2224/17519 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/1432 ,  H01L2924/1434

Abstract: Thermal heat spreaders and/or an IC die with solderable thermal structures may be assembled together with a solder array thermal interconnects. A thermal heat spreader may include a non-metallic material and one or more metallized surfaces suitable for bonding to a solder alloy employed as thermal interface material between the heat spreader and an IC die. An IC die may include a metallized back-side surface similarly suitable for bonding to a thermal interconnect comprising a solder alloy. Metallization on the IC die and/or heat spreader may comprise a plurality of solderable structures. A multi-chip package may include multiple IC die having different die thickness that are accommodated by a z-height thickness variation in the thermal interconnects and/or the solderable structures of the IC die or heat spreader.

公开(公告)号：US11923267B2

公开(公告)日：2024-03-05

申请号：US16831076

申请日：2020-03-26

Applicant: Intel Corporation

Inventor： Debendra Mallik ,  Je-Young Chang ,  Ram Viswanath ,  Elah Bozorg-Grayeli ,  Ahmad Al Mohammad

IPC: H01L23/367 ,  H01L23/373 ,  H01L23/495

CPC classification number: H01L23/3672 ,  H01L23/373 ,  H01L23/49568

Abstract: Thermal heat spreaders and/or an IC die with solderable thermal structures may be assembled together with a solder array thermal interconnects. A thermal heat spreader may include a non-metallic material and one or more metallized surfaces suitable for bonding to a solder alloy employed as thermal interface material between the heat spreader and an IC die. An IC die may include a metallized back-side surface similarly suitable for bonding to a thermal interconnect comprising a solder alloy. Metallization on the IC die and/or heat spreader may comprise a plurality of solderable structures. A multi-chip package may include multiple IC die having different die thickness that are accommodated by a z-height thickness variation in the thermal interconnects and/or the solderable structures of the IC die or heat spreader.

公开(公告)号：US20220181262A1

公开(公告)日：2022-06-09

申请号：US17677130

申请日：2022-02-22

Applicant: Intel Corporation

Inventor： Sanka Ganesan ,  Ram Viswanath ,  Xavier Francois Brun ,  Tarek A. Ibrahim ,  Jason M. Gamba ,  Manish Dubey ,  Robert Alan May

IPC: H01L23/538 ,  H01L23/367 ,  H01L23/31 ,  H01L23/00

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic component may include a substrate having a first face and an opposing second face, wherein the substrate includes a through-substrate via (TSV); a first mold material region at the first face, wherein the first mold material region includes a first through-mold via (TMV) conductively coupled to the TSV; and a second mold material region at the second face, wherein the second mold material region includes a second TMV conductively coupled to the TSV.

公开(公告)号：US09674954B2

公开(公告)日：2017-06-06

申请号：US13826614

申请日：2013-03-14

Applicant: Intel Corporation

Inventor： Rajasekaran Swaminathan ,  Donald T. Tran ,  Brent S. Stone ,  Ram Viswanath

IPC: H05K1/11 ,  H05K1/14 ,  H05K1/18 ,  H05K1/02 ,  H01R12/62

CPC classification number: H05K1/11 ,  H01R12/62 ,  H05K1/0204 ,  H05K1/0298 ,  H05K1/111 ,  H05K1/117 ,  H05K1/181 ,  H05K2201/094 ,  H05K2201/10189 ,  H05K2201/10356 ,  H05K2201/10378 ,  Y02P70/611

Abstract: This disclosure relates generally to a chip package assembly arranged to be electrically coupled to a circuit board including a plurality of circuit board contacts. The chip package assembly may include a chip package including a first side and a second side, the second side including a first plurality of contacts arranged to be electrically coupled to the plurality of circuit board contacts and a second plurality of contacts arranged to be electrically coupled to a remote device via a connector assembly.