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    Embedded memory device and method for embedding memory device in a substrate
    1.
    发明授权
    Embedded memory device and method for embedding memory device in a substrate 有权

    公开(公告)号：US11562993B2

    公开(公告)日：2023-01-24

    申请号：US17222923

    申请日：2021-04-05

    Applicant: Intel Corporation

    Inventor： Andrew Collins

    IPC: H01L25/18 ,  H01L23/538 ,  H01L23/00 ,  G11C29/04 ,  H01L23/48 ,  H01L23/367 ,  H01L21/48 ,  H01L25/00 ,  H01L25/065 ,  H01L23/13

    Abstract: A system and method of providing high bandwidth and low latency memory architecture solutions for next generation processors is disclosed. The package contains a substrate, a memory device embedded in the substrate via EMIB processes and a processor disposed on the substrate partially over the embedded memory device. The I/O pads of the processor and memory device are vertically aligned to minimize the distance therebetween and electrically connected through EMIB uvias. An additional memory device is disposed on the substrate partially over the embedded memory device or on the processor. I/O signals are routed using a redistribution layer on the embedded memory device or an organic VHD redistribution layer formed over the embedded memory device when the additional memory device is laterally adjacent to the processor and the I/O pads of the processor and additional memory device are vertically aligned when the additional memory device is on the processor.

    Interconnect hub for dies
    4.
    发明授权
    Interconnect hub for dies 有权

    公开(公告)号：US11621223B2

    公开(公告)日：2023-04-04

    申请号：US16419374

    申请日：2019-05-22

    Applicant: Intel Corporation

    Inventor： Andrew Collins ,  Sujit Sharan ,  Jianyong Xie

    IPC: H01L23/522 ,  H01L21/768 ,  H01L23/48 ,  H01L25/065 ,  H01L25/00

    Abstract: Embodiments herein relate to systems, apparatuses, or processes for an interconnect hub for dies that includes a first side and a second side opposite the first side to couple with three or more dies, where the second side includes a plurality of electrical couplings to electrically couple at least one of the three or more dies to another of the three or more dies to facilitate data transfer between at least a subset of the three or more dies. The three or more dies may be tiled dies.

    Pitch translation architecture for semiconductor package including embedded interconnect bridge
    5.
    发明授权
    Pitch translation architecture for semiconductor package including embedded interconnect bridge 有权

    公开(公告)号：US11270942B2

    公开(公告)日：2022-03-08

    申请号：US16839393

    申请日：2020-04-03

    Applicant: Intel Corporation

    Inventor： Andrew Collins ,  Bharat P. Penmecha ,  Rajasekaran Swaminathan ,  Ram Viswanath

    IPC: H01L23/538 ,  H01L23/528 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18

    Abstract: Various embodiments relate to a semiconductor package. The semiconductor package includes a first die. The first die includes a first bridge interconnect region. The semiconductor package further includes a second die. The second die includes a second bridge interconnect region. The semiconductor package includes a bridge die. The bridge die includes a first contact area to connect to the first bridge interconnect region and a second contact area to connect to the second bridge interconnect region. In the semiconductor package, the first bridge interconnect region is larger than the second bridge interconnect region. Additionally, each of the first bridge interconnect region and the second bridge interconnect region include a plurality of conductive bumps. An average pitch between adjacent bumps of the first bridge interconnect region is larger than an average pitch between adjacent bumps of the second bridge interconnect region.

    PITCH TRANSLATION ARCHITECTURE FOR SEMICONDUCTOR PACKAGE INCLUDING EMBEDDED INTERCONNECT BRIDGE
    7.
    发明申请
    PITCH TRANSLATION ARCHITECTURE FOR SEMICONDUCTOR PACKAGE INCLUDING EMBEDDED INTERCONNECT BRIDGE 审中-公开

    公开(公告)号：US20190206792A1

    公开(公告)日：2019-07-04

    申请号：US15857515

    申请日：2017-12-28

    Applicant: Intel Corporation

    Inventor： Andrew Collins ,  Bharat P. Penmecha ,  Rajasekaran Swaminathan ,  Ram Viswanath

    IPC: H01L23/528 ,  H01L23/538 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00

    CPC classification number: H01L23/5385 ,  H01L23/49838 ,  H01L23/5383

    Abstract: Various embodiments relate to a semiconductor package. The semiconductor package includes a first die. The first die includes a first bridge interconnect region. The semiconductor package further includes a second die. The second die includes a second bridge interconnect region. The semiconductor package includes a bridge die. The bridge die includes a first contact area to connect to the first bridge interconnect region and a second contact area to connect to the second bridge interconnect region. In the semiconductor package, the first bridge interconnect region is larger than the second bridge interconnect region. Additionally, each of the first bridge interconnect region and the second bridge interconnect region include a plurality of conductive bumps. An average pitch between adjacent bumps of the first bridge interconnect region is larger than an average pitch between adjacent bumps of the second bridge interconnect region.

    Variable in-plane signal to ground reference configurations
    8.
    发明授权
    Variable in-plane signal to ground reference configurations 有权

    公开(公告)号：US11705390B2

    公开(公告)日：2023-07-18

    申请号：US16366034

    申请日：2019-03-27

    Applicant: Intel Corporation

    Inventor： Andrew Collins ,  Arghya Sain

    IPC: H01L23/66 ,  H01L23/498

    CPC classification number: H01L23/49838 ,  H01L23/66 ,  H01L2223/6616 ,  H01L2223/6638

    Abstract: Embodiments disclosed herein include electronic packages with improved differential signaling architectures. In an embodiment, the electronic package comprises a package substrate, where the package substrate comprises alternating metal layers and dielectric layers. In an embodiment, a first trace is embedded in the package substrate, where the first trace has a first thickness that extends from a first metal layer to a second metal layer. In an embodiment, the electronic package further comprises a first ground plane laterally adjacent to a first side of the first trace, and a second ground plane laterally adjacent to a second side of the first trace.

    Semiconductor packages with chiplets coupled to a memory device
    9.
    发明授权
    Semiconductor packages with chiplets coupled to a memory device 有权

    公开(公告)号：US11610862B2

    公开(公告)日：2023-03-21

    申请号：US16147560

    申请日：2018-09-28

    Applicant: Intel Corporation

    Inventor： Andrew Collins ,  Jianyong Xie

    IPC: H01L25/065 ,  H01L23/00 ,  H01L23/528

    Abstract: Apparatuses, devices and systems associated with semiconductor packages with chiplet and memory device coupling are disclosed herein. In embodiments, a semiconductor package may include a first chiplet, a second chiplet, and a memory device. The semiconductor package may further include an interconnect structure that couples the first chiplet to a first memory channel of the memory device and the second chiplet to a second memory channel of the memory device. Other embodiments may be described and/or claimed.

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