公开(公告)号：US11574851B2

公开(公告)日：2023-02-07

申请号：US16287116

申请日：2019-02-27

Applicant: Intel Corporation

Inventor： Aastha Uppal ,  Omkar Karhade ,  Ram Viswanath ,  Je-Young Chang ,  Weihua Tang ,  Nitin Deshpande ,  Mitul Modi ,  Edvin Cetegen ,  Sanka Ganesan ,  Yiqun Bai ,  Jan Krajniak ,  Kumar Singh

IPC: H01L23/00 ,  H01L23/367 ,  H01L23/373 ,  H01L23/427 ,  H01L25/18 ,  H01L21/56

Abstract: An apparatus is provided which comprises: a package substrate, an integrated circuit device coupled to a surface of the package substrate, a first material on the surface of the package substrate, the first material contacting one or more lateral sides of the integrated circuit device, the first material extending at least to a surface of the integrated circuit device opposite the package substrate, two or more separate fins over a surface of the integrated circuit device, the two or more fins comprising a second material having a different composition than the first material, and a third material having a different composition than the second material, the third material over the surface of the integrated circuit device and between the two or more fins. Other embodiments are also disclosed and claimed.

公开(公告)号：US20200294884A1

公开(公告)日：2020-09-17

申请号：US16355596

申请日：2019-03-15

Applicant: Intel Corporation

Inventor： Javed Shaikh ,  Je-Young Chang ,  Kelly Lofgreen ,  Weihua Tang ,  Aastha Uppal

IPC: H01L23/38 ,  H01L35/10 ,  H01L35/16 ,  H01L35/18 ,  H01L35/30

Abstract: An Integrated Circuit (IC) assembly, comprising an IC package coupled to a substrate, and a subassembly comprising a thermal interface layer. The thermal interface layer comprises a phase change material (PCM) over the IC package. At least one thermoelectric cooling (TEC) apparatus is thermally coupled to the thermal interface layer.

公开(公告)号：US12021016B2

公开(公告)日：2024-06-25

申请号：US16898196

申请日：2020-06-10

Applicant: Intel Corporation

Inventor： Chandra Mohan Jha ,  Pooya Tadayon ,  Aastha Uppal ,  Weihua Tang ,  Paul Diglio ,  Xavier Brun

IPC: H01L23/498 ,  H01L21/56 ,  H01L21/78 ,  H01L23/373 ,  H01L23/522

CPC classification number: H01L23/49833 ,  H01L21/561 ,  H01L21/78 ,  H01L23/3732 ,  H01L23/3738 ,  H01L23/5226

Abstract: Embodiments disclosed herein comprise a die and methods of forming a die. In an embodiment, a die comprises, a die substrate, wherein the die substrate has a first thermal conductivity, and a first layer over the die substrate, wherein the first layer has a second thermal conductivity that is greater than the first thermal conductivity. In an embodiment, the die further comprises a second layer over the first layer, wherein the second layer comprises transistors.

公开(公告)号：US11978689B2

公开(公告)日：2024-05-07

申请号：US18089537

申请日：2022-12-27

Applicant: Intel Corporation

Inventor： Shrenik Kothari ,  Chandra Mohan Jha ,  Weihua Tang ,  Robert Sankman ,  Xavier Brun ,  Pooya Tadayon

IPC: H01L23/42 ,  H01L23/367 ,  H01L23/373 ,  H01L23/522 ,  H01L23/00 ,  H01L23/495 ,  H01L23/538 ,  H01L25/07

CPC classification number: H01L23/42 ,  H01L23/367 ,  H01L23/3738 ,  H01L23/522 ,  H01L23/49575 ,  H01L23/5384 ,  H01L24/20 ,  H01L25/072

Abstract: Embodiments disclosed herein include semiconductor dies and methods of forming such dies. In an embodiment, the semiconductor die comprises a semiconductor substrate, an active device layer in the semiconductor substrate, where the active device layer comprises one or more transistors, an interconnect layer over a first surface of the active device layer, a first bonding layer over a surface of the semiconductor substrate, a second bonding layer secured to the first bonding layer, and a heat spreader attached to the second bonding layer.

公开(公告)号：US11948906B2

公开(公告)日：2024-04-02

申请号：US16785014

申请日：2020-02-07

Applicant: INTEL CORPORATION

Inventor： Feras Eid ,  Joe Walczyk ,  Weihua Tang ,  Akhilesh Rallabandi ,  Marco Aurelio Cartas Ayala

IPC: H01L23/00

CPC classification number: H01L24/29 ,  H01L2224/29287 ,  H01L2224/29293 ,  H01L2224/29324 ,  H01L2224/29339 ,  H01L2224/29347 ,  H01L2924/14 ,  H01L2924/351

Abstract: An integrated circuit (IC) die structure comprises a substrate material comprising silicon. Integrated circuitry is over a first side of the substrate material. A composite layer is in direct contact with a second side of the substrate material. The second side is opposite the first side. The composite layer comprises a first constituent material associated with a first linear coefficient of thermal expansion (CTE), and a first thermal conductivity exceeding that of the substrate. The composite layer also comprises a second constituent material associated with a second CTE that is lower than the first, and a second thermal conductivity exceeding that of the substrate.

公开(公告)号：US20200219789A1

公开(公告)日：2020-07-09

申请号：US16241108

申请日：2019-01-07

Applicant: Intel Corporation

Inventor： Aastha Uppal ,  Je-Young Chang ,  Javed Shaikh ,  Divya Mani ,  Weihua Tang

IPC: H01L23/427 ,  H01L23/522 ,  H01L21/48 ,  H01L23/00

Abstract: An integrated circuit structure may be formed using a phase change material to substantially fill at least one chamber within the integrated circuit assembly to increase thermal capacitance. The integrated circuit assembly may comprise a substrate, at least one integrated circuit device electrically attached to the substrate, a heat dissipation device, a thermal interface material between the integrated circuit device and the heat dissipation device, a chamber defined by the heat dissipation device, the substrate, and the integrated circuit device, and a phase change material within the chamber.

公开(公告)号：US20240203926A1

公开(公告)日：2024-06-20

申请号：US18593775

申请日：2024-03-01

Applicant: Intel Corporation

Inventor： Feras Eid ,  Joe Walczyk ,  Weihua Tang ,  Akhilesh Rallabandi ,  Marco Aurelio Cartas Ayala

IPC: H01L23/00

CPC classification number: H01L24/29 ,  H01L2224/29287 ,  H01L2224/29293 ,  H01L2224/29324 ,  H01L2224/29339 ,  H01L2224/29347 ,  H01L2924/14 ,  H01L2924/351

Abstract: An integrated circuit (IC) die structure comprises a substrate material comprising silicon. Integrated circuitry is over a first side of the substrate material. A composite layer is in direct contact with a second side of the substrate material. The second side is opposite the first side. The composite layer comprises a first constituent material associated with a first linear coefficient of thermal expansion (CTE), and a first thermal conductivity exceeding that of the substrate. The composite layer also comprises a second constituent material associated with a second CTE that is lower than the first, and a second thermal conductivity exceeding that of the substrate.

公开(公告)号：US11756860B2

公开(公告)日：2023-09-12

申请号：US16522443

申请日：2019-07-25

Applicant: Intel Corporation

Inventor： Shrenik Kothari ,  Chandra Mohan Jha ,  Weihua Tang ,  Robert Sankman ,  Xavier Brun ,  Pooya Tadayon

IPC: H01L23/42 ,  H01L23/522 ,  H01L23/373 ,  H01L23/367 ,  H01L25/07 ,  H01L23/538

CPC classification number: H01L23/42 ,  H01L23/367 ,  H01L23/3738 ,  H01L23/522 ,  H01L23/5384 ,  H01L25/072

Abstract: Embodiments disclosed herein include semiconductor dies and methods of forming such dies. In an embodiment, the semiconductor die comprises a semiconductor substrate, an active device layer in the semiconductor substrate, where the active device layer comprises one or more transistors, an interconnect layer over a first surface of the active device layer, a first bonding layer over a surface of the semiconductor substrate, a second bonding layer secured to the first bonding layer, and a heat spreader attached to the second bonding layer.

公开(公告)号：US11626395B2

公开(公告)日：2023-04-11

申请号：US17462794

申请日：2021-08-31

Applicant: Intel Corporation

Inventor： Robert L. Sankman ,  Pooya Tadayon ,  Weihua Tang ,  Chandra M. Jha ,  Zhimin Wan

IPC: H01L25/18 ,  H01L23/48 ,  H01L23/42 ,  H01L23/00

Abstract: An electronic device and associated methods are disclosed. In one example, the electronic device includes a plurality of dies, a logic die coupled to the plurality of dies, and a dummy die thereon. In selected examples, the dummy die is located between the logic die and the plurality of silicon dies. In selected examples, the dummy die is attached to the logic die.

公开(公告)号：US11127727B2

公开(公告)日：2021-09-21

申请号：US16433756

申请日：2019-06-06

Applicant: Intel Corporation

Inventor： Robert L. Sankman ,  Pooya Tadayon ,  Weihua Tang ,  Chandra M. Jha ,  Zhimin Wan

IPC: H01L25/18 ,  H01L23/48 ,  H01L23/42 ,  H01L23/00

Abstract: An electronic device and associated methods are disclosed. In one example, the electronic device includes a plurality of dies, a logic die coupled to the plurality of dies, and a dummy die thereon. In selected examples, the dummy die is located between the logic die and the plurality of silicon dies. In selected examples, the dummy die is attached to the logic die.