公开(公告)号：US20190104610A1

公开(公告)日：2019-04-04

申请号：US15720488

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Robert Nickerson ,  Nitin Deshpande ,  Omkar Karhade ,  Thomas De Bonis

IPC: H05K1/02 ,  H05K1/14 ,  H05K3/00

Abstract: Methods/structures of joining package structures are described. Those methods/structures may include a first substrate comprising a first die, wherein an underfill material is disposed on a first surface of the first substrate adjacent the first die; and a second substrate disposed on the first substrate, wherein the second substrate comprises at least one opening disposed over the first die, wherein the at least one opening is at least partially filled with the underfill material.

公开(公告)号：US20160043049A1

公开(公告)日：2016-02-11

申请号：US14879418

申请日：2015-10-09

Applicant: Intel Corporation

Inventor： Chia-Pin Chiu ,  Xiaorong Xiong ,  Linda Zhang ,  Robert Nickerson ,  Charles Gealer

IPC: H01L23/00 ,  H01L25/065 ,  H01L21/56

CPC classification number: H01L24/13 ,  H01L21/565 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49827 ,  H01L24/11 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/11013 ,  H01L2224/1132 ,  H01L2224/13014 ,  H01L2224/13082 ,  H01L2224/16225 ,  H01L2224/1703 ,  H01L2225/0652 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/1533 ,  H01L2924/1815 ,  H01L2924/00

Abstract: Generally discussed herein are systems and apparatuses that include an extended TSBA ball and techniques for making the same. According to an example, a technique can include forming a circuit substrate including forming a circuit on a substrate, the circuit exposed along an upper surface of the substrate, wherein the substrate is for coupling the circuit with a die along a lower surface of the circuit substrate. A molding can be formed onto an upper surface of the circuit substrate, over the circuit of the circuit substrate. An opening can be defined in the molding so that the opening can extend to a top surface of the molding to at least a portion of the circuit. Solder can be formed into the opening, including conforming the solder to the opening and the circuit substrate.

公开(公告)号：US09159690B2

公开(公告)日：2015-10-13

申请号：US14036755

申请日：2013-09-25

Applicant: Intel Corporation

Inventor： Chia-Pin Chiu ,  Xiaorong Xiong ,  Linda Zhang ,  Robert Nickerson ,  Charles Gealer

IPC: H01L23/00

CPC classification number: H01L24/13 ,  H01L21/565 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49827 ,  H01L24/11 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/11013 ,  H01L2224/1132 ,  H01L2224/13014 ,  H01L2224/13082 ,  H01L2224/16225 ,  H01L2224/1703 ,  H01L2225/0652 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/1533 ,  H01L2924/1815 ,  H01L2924/00

Abstract: Generally discussed herein are systems and apparatuses that include an extended TSBA ball and techniques for making the same. A package can include a chip package situated below a lower surface of a first substrate, the package including a die situated on a top surface of a second substrate, a molding disposed over the upper surface of the second substrate, the molding extending over the second die and including an opening extending from an upper surface of the molding towards an upper surface of the second substrate, wherein the opening is configured to admit at least a portion of the solder ball, and a solder column electrically and mechanically coupled to the second substrate, situated in the opening, conforming to the cylinder, and including at least two layers of solder with flux therebetween.

Abstract translation: 本文通常讨论的是包括扩展TSBA球的系统和装置及其制造技术。 封装可以包括位于第一基板的下表面下方的芯片封装，所述封装包括位于第二基板的顶表面上的模具，设置在所述第二基板的上表面上的模具，所述模制件在所述第二基板的上表面上延伸 并且包括从模制件的上表面朝向第二基板的上表面延伸的开口，其中开口被配置为允许焊球的至少一部分，并且焊料柱电和机械地耦合到第二基板 ，位于开口中，符合气缸，并且包括至少两层焊料，焊剂之间具有焊剂。

公开(公告)号：US11430724B2

公开(公告)日：2022-08-30

申请号：US16646529

申请日：2017-12-30

Applicant: Intel Corporation

Inventor： Debendra Mallik ,  Robert L. Sankman ,  Robert Nickerson ,  Mitul Modi ,  Sanka Ganesan ,  Rajasekaran Swaminathan ,  Omkar Karhade ,  Shawna M. Liff ,  Amruthavalli Alur ,  Sri Chaitra J. Chavali

IPC: H01L23/52 ,  H01L23/498 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00

Abstract: Ultra-thin, hyper-density semiconductor packages and techniques of forming such packages are described. An exemplary semiconductor package is formed with one or more of: (i) metal pillars having an ultra fine pitch (e.g., a pitch that is greater than or equal to 150 μm, etc.); (ii) a large die to-package ratio (e.g., a ratio that is equal to or greater than 0.85, etc.); and (iii) a thin pitch translation interposer. Another exemplary semiconductor package is formed using coreless substrate technology, die back metallization, and low temperature solder technology for ball grid array (BGA) metallurgy. Other embodiments are described.

公开(公告)号：US20200251462A1

公开(公告)日：2020-08-06

申请号：US16679696

申请日：2019-11-11

Applicant: Intel Corporation

Inventor： Russell Mortensen ,  Robert Nickerson ,  Nicholas R. Watts

IPC: H01L25/18 ,  H01L25/065 ,  H01L25/00 ,  H01L23/00 ,  H01L23/498 ,  H01L21/48 ,  H05K3/40 ,  H05K1/11 ,  H01L25/10

Abstract: An offset interposer includes a land side including land-side ball-grid array (BGA) and a package-on-package (POP) side including a POP-side BGA. The land-side BGA includes two adjacent, spaced-apart land-side pads, and the POP-side BGA includes two adjacent, spaced-apart POP-side pads that are coupled to the respective two land-side BGA pads through the offset interposer. The land-side BGA is configured to interface with a first-level interconnect. The POP-side BGA is configured to interface with a POP substrate. Each of the two land-side pads has a different footprint than the respective two POP-side pads.

公开(公告)号：US09177911B2

公开(公告)日：2015-11-03

申请号：US14293916

申请日：2014-06-02

Applicant: Intel Corporation

Inventor： Robert Nickerson ,  Nicholas Holmberg

IPC: H01L23/02 ,  H01L23/522 ,  H01L23/498 ,  H01L23/538 ,  H01L23/31 ,  H01L25/03 ,  H01L25/065 ,  H01L25/10

CPC classification number: H01L23/5226 ,  H01L23/3107 ,  H01L23/49827 ,  H01L23/5389 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/16145 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2224/73215 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06568

Abstract: This disclosure relates generally to package substrates with multiple embedded dice wherein each of the embedded dice can be connected directly to a bus of the package substrate without being routed through another die. The package substrate may be configured as a bumpless build up layer (BBUL) substrate.

Abstract translation: 本公开一般涉及具有多个嵌入式裸片的封装衬底，其中每个嵌入的裸片可以直接连接到封装衬底的总线，而不通过另一个裸片布线。 封装衬底可以被配置为无凸起构建层（BBUL）衬底。

公开(公告)号：US20230197659A1

公开(公告)日：2023-06-22

申请号：US17556444

申请日：2021-12-20

Applicant: Intel Corporation

Inventor： Mukund Ayalasomayajula ,  Dinesh Padmanabhan Ramalekshmi Thanu ,  Rui Zhang ,  Xiao Lu ,  Robert Nickerson ,  Patrick Neel Stover

IPC: H01L23/00

CPC classification number: H01L24/16 ,  H01L24/03 ,  H01L24/81 ,  H01L2924/1432 ,  H01L2924/0105 ,  H01L2924/01029 ,  H01L2924/01047

Abstract: A die package comprises a substrate comprising a solder pad element, a semiconductor die coupled to the substrate, a solder layer comprising a first solder material deposited on the solder pad element, the first solder material having a first melting temperature, and an interconnect ball comprising a second solder material deposited on the solder layer, the second solder material having a second melting temperature that is less than the first melting temperature.

公开(公告)号：US11462527B2

公开(公告)日：2022-10-04

申请号：US16049696

申请日：2018-07-30

Applicant: Intel Corporation

Inventor： Kumar Abhishek Singh ,  Zhaozhi Li ,  Thomas J. Debonis ,  Robert Nickerson ,  Rees Winters

IPC: H01L23/48 ,  H01L25/18 ,  H01L23/31 ,  H01L21/56 ,  H01L21/48 ,  H01L23/544 ,  H01L25/00

Abstract: Embodiments disclosed herein include an electronics package. In an embodiment, the electronics package comprises a package substrate and a die on the package substrate. In an embodiment, a mold layer is positioned over the package substrate. In an embodiment, the electronics package further comprises through-mold interconnects through the mold layer, and a trench that extends at least partially into the mold layer.

公开(公告)号：US10231338B2

公开(公告)日：2019-03-12

申请号：US14748496

申请日：2015-06-24

Applicant: INTEL CORPORATION

Inventor： Naga Sivakumar Yagnamurthy ,  Huiyang Fei ,  Pramod Malatkar ,  Prasanna Raghavan ,  Robert Nickerson

IPC: H01L23/28 ,  H01L23/538 ,  H01L25/065 ,  H05K1/18 ,  H05K1/11 ,  B29C70/84 ,  B29C70/70 ,  B29C70/88 ,  B29C37/00 ,  B29C33/00 ,  B29C69/00 ,  G11C11/401 ,  H01L23/48 ,  H01L23/498 ,  H01L25/10 ,  B29K63/00 ,  B29L31/34 ,  G11C5/04 ,  H05K1/14

Abstract: Methods of forming a package structures comprising a trench are described. An embodiment includes a first die disposed on a first substrate, and at least one interconnect structure disposed on a peripheral region of the first substrate. A molding compound is disposed on a portion of the first substrate and on the first die, wherein a trench opening is disposed in the molding compound that is located between the at least one interconnect structure and the first die.

公开(公告)号：US09666549B2

公开(公告)日：2017-05-30

申请号：US14879418

申请日：2015-10-09

Applicant: Intel Corporation

Inventor： Chia-Pin Chiu ,  Xiaorong Xiong ,  Linda Zhang ,  Robert Nickerson ,  Charles Gealer

IPC: H01L23/00 ,  H01L25/10 ,  H01L23/498 ,  H01L25/00 ,  H01L21/56 ,  H01L25/065 ,  H01L23/31

CPC classification number: H01L24/13 ,  H01L21/565 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49827 ,  H01L24/11 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/11013 ,  H01L2224/1132 ,  H01L2224/13014 ,  H01L2224/13082 ,  H01L2224/16225 ,  H01L2224/1703 ,  H01L2225/0652 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/1533 ,  H01L2924/1815 ,  H01L2924/00

Abstract: Generally discussed herein are systems and apparatuses that include an extended TSBA ball and techniques for making the same. According to an example, a technique can include forming a circuit substrate including forming a circuit on a substrate, the circuit exposed along an upper surface of the substrate, wherein the substrate is for coupling the circuit with a die along a lower surface of the circuit substrate. A molding can be formed onto an upper surface of the circuit substrate, over the circuit of the circuit substrate. An opening can be defined in the molding so that the opening can extend to a top surface of the molding to at least a portion of the circuit. Solder can be formed into the opening, including conforming the solder to the opening and the circuit substrate.