公开(公告)号：US12191220B2

公开(公告)日：2025-01-07

申请号：US16659395

申请日：2019-10-21

Applicant: Intel Corporation

Inventor： Zhimin Wan ,  Chandra Mohan Jha ,  Je-Young Chang ,  Chia-Pin Chiu

IPC: H01L23/15 ,  H01L23/00 ,  H01L23/373 ,  H01L23/498 ,  H01L25/18

Abstract: Embodiments include semiconductor packages. A semiconductor package includes a hybrid interposer with a first region and a second region. The first region is comprised of glass or low thermal conductive materials, and the second region is comprised of silicon or diamond materials. The semiconductor package includes a first die on the first region of the hybrid interposer, a second die on the second region of the hybrid interposer, and an integrated heat spreader over the first die, the second die, and the hybrid interposer. The hybrid interposer includes first and second interconnects, where the first interconnects vertically extend from a bottom surface of the first region to a top surface of the first region, and where the second interconnects vertically extend from a bottom surface of the second region to a top surface of the second region. The first interconnects are through-glass vias, and the second interconnects are through-silicon vias.

公开(公告)号：US20240319457A1

公开(公告)日：2024-09-26

申请号：US18189911

申请日：2023-03-24

Applicant: Intel Corporation

Inventor： Chia-Pin Chiu ,  Kaveh Hosseini

IPC: G02B6/42

CPC classification number: G02B6/4273 ,  G02B6/4238 ,  G02B6/4274

Abstract: In one embodiment, a photonic integrated circuit (PIC) device includes conductive pads on a surface of the PIC and a micro ring resonator (MRR) with a heater element centrally located between the conductive pads. The PIC also includes a cavity defined within a substrate of the PIC below the MRR, and a plurality of holes defined between the MRR and the conductive pads. The holes extend from a top surface of the PIC into the cavity, and each hole is between a respective conductive pad and the MRR.

公开(公告)号：US12051667B2

公开(公告)日：2024-07-30

申请号：US18373849

申请日：2023-09-27

Applicant: Intel Corporation

Inventor： Weng Hong Teh ,  Chia-Pin Chiu

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/31 ,  H01L23/50 ,  H01L25/16 ,  H01L25/18 ,  H01L21/56

CPC classification number: H01L24/25 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/50 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L25/16 ,  H01L25/18 ,  H01L21/568 ,  H01L23/3128 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/2501 ,  H01L2224/2505 ,  H01L2224/2512 ,  H01L2224/255 ,  H01L2224/73209 ,  H01L2224/81005 ,  H01L2224/92133 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/141 ,  H01L2924/1431 ,  H01L2924/1461 ,  H01L2924/15151 ,  H01L2924/15192 ,  H01L2924/15747 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/1461 ,  H01L2924/00 ,  H01L2924/15747 ,  H01L2924/00 ,  H01L2924/12042 ,  H01L2924/00

Abstract: Discussed generally herein are devices that include high density interconnects between dice and techniques for making and using those devices. In one or more embodiments a device can include a bumpless buildup layer (BBUL) substrate including a first die at least partially embedded in the BBUL substrate, the first die including a first plurality of high density interconnect pads. A second die can be at least partially embedded in the BBUL substrate, the second die including a second plurality of high density interconnect pads. A high density interconnect element can be embedded in the BBUL substrate, the high density interconnect element including a third plurality of high density interconnect pads electrically coupled to the first and second plurality of high density interconnect pads.

公开(公告)号：US11837519B2

公开(公告)日：2023-12-05

申请号：US16783819

申请日：2020-02-06

Applicant: Intel Corporation

Inventor： Zhimin Wan ,  Chia-Pin Chiu ,  Chandra Mohan Jha

IPC: H01L23/15 ,  H01L23/367 ,  H01L25/065 ,  H01L23/538 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L23/367 ,  H01L23/5386 ,  H01L25/0652 ,  H01L23/49816 ,  H01L23/5384 ,  H01L24/16 ,  H01L2224/16221

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises an interposer, a first die attached to the interposer, and a second die attached to the interposer. In an embodiment, the electronic package further comprises a heatsink thermally coupled to the first die and the second die. In an embodiment, the heatsink has a first surface facing away from the first die and the second die and a second surface facing the first die and the second die. In an embodiment, the heatsink comprises a thermal break between the first die and the second die.

公开(公告)号：US11140770B2

公开(公告)日：2021-10-05

申请号：US15927020

申请日：2018-03-20

Applicant: Intel Corporation

Inventor： Chia-Pin Chiu

IPC: H05K1/02 ,  H05K1/18 ,  H05K5/00 ,  H05K1/11 ,  H01G4/12 ,  H05K3/30

Abstract: Printed circuit board assembly (PCBA) technology is disclosed. A PCBA can include a printed circuit board (PCB). The PCBA can also include a capacitor operably mounted on a side of the PCB. In addition, the PCBA can include a damper material coupled to the PCB and operable to dissipate kinetic energy generated by the capacitor during operation. An electronic system including a capacitor and damping material, and a method for minimizing acoustic vibration in an electronic system are also disclosed.

公开(公告)号：US20200303852A1

公开(公告)日：2020-09-24

申请号：US16361537

申请日：2019-03-22

Applicant: Intel Corporation

Inventor： Zhimin Wan ,  Steven A. Klein ,  Chia-Pin Chiu ,  Shankar Devasenathipathy

IPC: H01R12/70 ,  H01R12/71 ,  H01R13/24 ,  H01R13/50

Abstract: An integrated circuit (IC) socket comprising a housing with a land side, an opposing die side, and sidewalls around a perimeter of the housing. The housing comprises a first dielectric. A plurality of socket pins extends from the land side of the housing through socket pin holes in the housing over the die side of the housing. A second dielectric is within the interstitial regions between the socket pins and sidewalls of the socket pin holes. A frame structure extends around at least a portion of the perimeter of the housing, and a mesh structure is embedded within the first dielectric. The mesh structure has plurality of mesh filaments extending between the plurality of socket pin holes and coupled to the frame structure.

公开(公告)号：US10008475B2

公开(公告)日：2018-06-26

申请号：US13629368

申请日：2012-09-27

Applicant: Intel Corporation

Inventor： Chia-Pin Chiu

IPC: H01L23/02 ,  H01L23/34 ,  H01L23/48 ,  H01L23/52 ,  H01L21/44 ,  H01L21/48 ,  H01L21/50 ,  H01L25/065 ,  H01L23/13 ,  H01L23/36 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L23/13 ,  H01L23/36 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/16 ,  H01L2224/13111 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/17051 ,  H01L2224/29109 ,  H01L2224/2929 ,  H01L2224/29339 ,  H01L2224/32135 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81815 ,  H01L2225/06513 ,  H01L2924/00012 ,  H01L2924/1515 ,  H01L2924/15321 ,  H01L2924/171 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/0665 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00

Abstract: Some embodiments described herein include apparatuses and methods of forming such apparatuses. In one such embodiment, an apparatus may include a substrate, a first die, and a second die coupled to the first die and the substrate. The substrate may include an opening. At least a portion of the die may occupy at least a portion of the opening in the substrate. Other embodiments including additional apparatuses and methods are described.

公开(公告)号：US09589866B2

公开(公告)日：2017-03-07

申请号：US15046280

申请日：2016-02-17

Applicant: Intel Corporation

Inventor： Chia-Pin Chiu ,  Zhiguo Qian ,  Mathew J. Manusharow

IPC: H01L29/00 ,  H01L23/482 ,  H01L23/00 ,  H01L23/538 ,  H01L25/065 ,  H01L21/02 ,  H01L21/306 ,  H01L21/768

CPC classification number: H01L23/5385 ,  H01L21/02164 ,  H01L21/30604 ,  H01L21/486 ,  H01L21/768 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/4821 ,  H01L23/5381 ,  H01L23/5382 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/1433 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2224/0401

Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for a bridge interconnect assembly that can be embedded in a package assembly. In one embodiment, a package assembly includes a package substrate configured to route electrical signals between a first die and a second die and a bridge embedded in the package substrate and configured to route the electrical signals between the first die and the second die, the bridge including a bridge substrate, one or more through-hole vias (THVs) formed through the bridge substrate, and one or more traces disposed on a surface of the bridge substrate to route the electrical signals between the first die and the second die. Routing features including traces and a ground plane of the bridge interconnect assembly may be separated by an air gap. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例涉及可嵌入封装组件中的桥互连组件的技术和配置。 在一个实施例中，包装组件包括被配置为在第一管芯和第二管芯之间布置电信号的封装衬底和嵌入在封装衬底中并被配置为在第一管芯和第二管芯之间布置电信号的桥， 包括桥接基板，通过桥接基板形成的一个或多个通孔通孔（THV）和布置在桥接基板的表面上的一个或多个走线，以在第一管芯和第二管芯之间布置电信号。 包括迹线和桥互连组件的接地平面的布线特征可以由气隙分开。 可以描述和/或要求保护其他实施例。

公开(公告)号：US09269701B2

公开(公告)日：2016-02-23

申请号：US14818902

申请日：2015-08-05

Applicant: Intel Corporation

Inventor： Robert Starkston ,  Debendra Mallik ,  John S. Guzek ,  Chia-Pin Chiu ,  Deepak Kulkarni ,  Ravi V. Mahajan

IPC: H01L21/44 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L23/5226 ,  H01L21/563 ,  H01L23/5385 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L25/0655 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05541 ,  H01L2224/05568 ,  H01L2224/0603 ,  H01L2224/131 ,  H01L2224/1403 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/83102 ,  H01L2924/12042 ,  H01L2924/15192 ,  H01L2924/00014 ,  H01L2924/206 ,  H01L2924/014 ,  H01L2924/00

Abstract: Embodiments of a system and methods for localized high density substrate routing are generally described herein. In one or more embodiments an apparatus includes a medium, first and second circuitry elements, an interconnect element, and a dielectric layer. The medium can include low density routing therein. The interconnect element can be embedded in the medium, and can include a plurality of electrically conductive members therein, the electrically conductive member can be electrically coupled to the first circuitry element and the second circuitry element. The interconnect element can include high density routing therein. The dielectric layer can be over the interconnect die, the dielectric layer including the first and second circuitry elements passing therethrough.

公开(公告)号：US12176676B2

公开(公告)日：2024-12-24

申请号：US17076443

申请日：2020-10-21

Applicant: Intel Corporation

Inventor： Chia-Pin Chiu

IPC: H01S3/04 ,  H01S5/023 ,  H01S5/024 ,  H01S5/042

Abstract: Embodiments disclosed herein include dual sided cooling architectures for laser packages. In an embodiment, an electronic package comprises a package substrate, and a laser chip attached to the package substrate. In an embodiment, the laser chip has a first surface and a second surface opposite from the first surface. In an embodiment, an interposer is disposed over the laser chip, where the interposer overhangs an edge of the laser chip. In an embodiment, the electronic package further comprises an interconnect between the interposer and the package substrate.