公开(公告)号：US20240290761A1

公开(公告)日：2024-08-29

申请号：US18439276

申请日：2024-02-12

申请人： Amkor Technology Singapore Holding Pte. Ltd.

发明人： Bora Baloglu ,  Ron Huemoeller ,  Curtis Zwenger

IPC分类号： H01L25/10 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/36 ,  H01L23/367 ,  H01L23/373 ,  H01L23/538 ,  H01L23/552 ,  H01L25/00 ,  H01L25/065

CPC分类号： H01L25/105 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/4882 ,  H01L21/565 ,  H01L23/36 ,  H01L23/367 ,  H01L23/3672 ,  H01L23/3675 ,  H01L23/3677 ,  H01L23/3736 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/19 ,  H01L24/20 ,  H01L25/0657 ,  H01L25/50 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L2224/0401 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/214 ,  H01L2224/32135 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/81203 ,  H01L2224/81224 ,  H01L2224/81815 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2225/06589 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/1433 ,  H01L2924/14335 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/3025 ,  H01L2924/3511

摘要： A semiconductor package having an internal heat distribution layer and methods of forming the semiconductor package are provided. The semiconductor package can include a first semiconductor device, a second semiconductor device, and an external heat distribution layer. The first semiconductor device can comprise a first semiconductor die and an external surface comprising a top surface, a bottom surface, and a side surface joining the bottom surface to the tope surface. The second semiconductor device can comprise a second semiconductor die and can be stacked on the top surface of the first semiconductor device. The external heat distribution layer can cover an external surface of the second semiconductor device and the side surface of the first semiconductor device. The external heat distribution layer further contacts an internal heat distribution layer on a top surface of the first semiconductor die.

公开(公告)号：US09357652B2

公开(公告)日：2016-05-31

申请号：US14568603

申请日：2014-12-12

申请人： Samsung Electronics Co., Ltd.

发明人： Hee Jeong Kim ,  Yong Kwan Lee

IPC分类号： H01L21/48 ,  H01L21/52 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H05K3/06 ,  H01L23/13 ,  H01L23/498 ,  H01L23/14

CPC分类号： H05K3/06 ,  H01L21/486 ,  H01L21/52 ,  H01L23/13 ,  H01L23/145 ,  H01L23/3128 ,  H01L23/49827 ,  H01L24/16 ,  H01L24/32 ,  H01L24/43 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/85 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/29036 ,  H01L2224/32135 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/451 ,  H01L2224/48106 ,  H01L2224/48228 ,  H01L2224/48235 ,  H01L2224/49176 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06548 ,  H01L2225/06568 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/15153 ,  H01L2924/15156 ,  H01L2924/152 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15331 ,  H05K1/144 ,  H05K1/183 ,  H05K3/4697 ,  H05K2201/041 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2224/48227 ,  H01L2924/00012

摘要： A method of manufacturing a circuit board may include: preparing a circuit board body including an insulating layer having a first surface and a second surface opposite to the first surface and a first conductive thin film layer disposed on the first surface of the insulating layer and having a convex portion which is disposed on a first surface of the first conductive thin film layer and is embedded in the insulating layer; removing the convex portion to form a cavity corresponding to the convex portion in the insulating layer; and forming one or more first wiring patterns on the first surface of the insulating layer by removing first portions of the first conductive thin film layer. The one or more first wiring patterns correspond to second portions of the first conductive thin film layer not removed.

摘要翻译： 制造电路板的方法可以包括：制备电路板主体，其包括具有第一表面和与第一表面相对的第二表面的绝缘层，以及设置在绝缘层的第一表面上的第一导电薄膜层，并且具有 凸部，其设置在所述第一导电性薄膜层的第一表面上并嵌入所述绝缘层中; 去除所述凸部以形成与所述绝缘层中的所述凸部对应的空腔; 以及通过去除第一导电薄膜层的第一部分，在绝缘层的第一表面上形成一个或多个第一布线图案。 一个或多个第一布线图案对应于未被去除的第一导电薄膜层的第二部分。

公开(公告)号：US20150364449A1

公开(公告)日：2015-12-17

申请号：US14833840

申请日：2015-08-24

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Zheng-Yi Lim ,  Yi-Wen Wu ,  Tzong-Hann Yang ,  Ming-Che Ho ,  Chung-Shi Liu

IPC分类号： H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498

CPC分类号： H01L24/81 ,  H01L21/56 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49833 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/13016 ,  H01L2224/13017 ,  H01L2224/13018 ,  H01L2224/13023 ,  H01L2224/13124 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13582 ,  H01L2224/13583 ,  H01L2224/13611 ,  H01L2224/13644 ,  H01L2224/13647 ,  H01L2224/13655 ,  H01L2224/13657 ,  H01L2224/13664 ,  H01L2224/16148 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/16501 ,  H01L2224/16505 ,  H01L2224/32135 ,  H01L2224/32141 ,  H01L2224/32145 ,  H01L2224/81085 ,  H01L2224/811 ,  H01L2224/8112 ,  H01L2224/81121 ,  H01L2224/81193 ,  H01L2224/81232 ,  H01L2224/81355 ,  H01L2224/81359 ,  H01L2224/81801 ,  H01L2224/8192 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/1533 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2924/3841 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/01005 ,  H01L2924/01074 ,  H01L2924/01015 ,  H01L2924/06 ,  H01L2924/00

摘要： A method includes aligning a first electrical connector of a first package component to a second electrical connector of a second package component. With the first electrical connector aligned to the second electrical connector, a metal layer is plated on the first and the second electrical connectors. The metal layer bonds the first electrical connector to the second electrical connector.

摘要翻译： 一种方法包括将第一包装部件的第一电连接器与第二包装部件的第二电连接器对准。 利用第一电​​连接器与第二电连接器对准，金属层被电镀在第一和第二电连接器上。 金属层将第一电连接器连接到第二电连接器。

公开(公告)号：US09129947B2

公开(公告)日：2015-09-08

申请号：US13973132

申请日：2013-08-22

申请人： Silergy Semiconductor Technology (Hangzhou) LTD

发明人： Xiaochun Tan ,  Wei Chen

IPC分类号： H01L23/495 ,  H01L23/00 ,  H01L23/31

CPC分类号： H01L23/495 ,  H01L23/3107 ,  H01L23/49575 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/80 ,  H01L24/92 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/29006 ,  H01L2224/2919 ,  H01L2224/32135 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： In one embodiment, a multi-chip packaging structure can include: (i) N chips, where N is an integer of at least two, and where an upper surface of each chip can include a plurality of pads; (ii) a lead frame with a chip carrier and a plurality of pins, where the N chips are stacked in layers on the chip carrier, and where a chip in an upper layer partially covers a chip in a lower layer such that the plurality of pads of the lower layer chip are exposed; (iii) a plurality of first bonding leads that can connect pads on one chip to pads on another chip; and (iv) a plurality of second bonding leads that can connect pads on at least one chip to the plurality of pins for external connection to the multi-chip packaging structure.

摘要翻译： 在一个实施例中，多芯片封装结构可以包括：（i）N个芯片，其中N是至少为2的整数，并且每个芯片的上表面可以包括多个焊盘; （ii）具有芯片载体和多个引脚的引线框架，其中N个芯片层叠在芯片载体上，并且其中上层中的芯片部分地覆盖下层中的芯片，使得多个 下层芯片的焊盘露出; （iii）可以将一个芯片上的焊盘连接到另一个芯片上的焊盘的多个第一焊接引线; 以及（iv）多个第二接合引线，其可将至少一个芯片上的焊盘连接到所述多个引脚以用于与所述多芯片封装结构的外部连接。

公开(公告)号：US20140206142A1

公开(公告)日：2014-07-24

申请号：US14225647

申请日：2014-03-26

申请人： Thorsten Meyer

发明人： Thorsten Meyer

IPC分类号： H01L23/00

CPC分类号： H01L24/96 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/24 ,  H01L24/73 ,  H01L24/81 ,  H01L24/82 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/24225 ,  H01L2224/2919 ,  H01L2224/32135 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/81005 ,  H01L2224/83005 ,  H01L2224/83862 ,  H01L2224/92225 ,  H01L2224/92244 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06558 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/0401

摘要： An electronic package includes a flip-chip component having a first die coupled to a flip-chip substrate, second die stacked on the first die, an encapsulation compound formed around the first die and the second die, a set of through encapsulant vias (TEVs) providing a set of electrical connections from a first side of the electronic package to a second side of the electronic package through the encapsulation compound to the flip-chip substrate, and a redistribution layer electrically connecting a set of contacts on the second die to the set of TEVs on the first side of the electronic package.

摘要翻译： 电子封装包括倒装芯片组件，其具有耦合到倒装芯片衬底的第一管芯，堆叠在第一管芯上的第二管芯，形成在第一管芯和第二管芯周围的封装化合物，一组通过封装通孔（TEV ）提供从电子封装的第一侧到电子封装的第二侧的一组电连接，通过封装化合物到倒装芯片衬底，以及再分配层，将第二裸片上的一组触点电连接到 在电子包装的第一面设置一组TEV。

公开(公告)号：US11901343B2

公开(公告)日：2024-02-13

申请号：US17233983

申请日：2021-04-19

申请人： Amkor Technology Singapore Holding Pte. Ltd.

发明人： Bora Baloglu ,  Ron Huemoeller ,  Curtis Zwenger

IPC分类号： H01L23/495 ,  H01L25/10 ,  H01L23/373 ,  H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00 ,  H01L23/552 ,  H01L23/00 ,  H01L23/367 ,  H01L23/36 ,  H01L25/065

CPC分类号： H01L25/105 ,  H01L21/486 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/4882 ,  H01L21/565 ,  H01L23/36 ,  H01L23/367 ,  H01L23/3672 ,  H01L23/3675 ,  H01L23/3677 ,  H01L23/3736 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/19 ,  H01L24/20 ,  H01L25/0657 ,  H01L25/50 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L2224/0401 ,  H01L2224/131 ,  H01L2224/13082 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/214 ,  H01L2224/32135 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/81203 ,  H01L2224/81224 ,  H01L2224/81815 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2225/06589 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/14335 ,  H01L2924/15311 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/3025 ,  H01L2924/3511 ,  H01L2224/97 ,  H01L2224/81 ,  H01L2224/131 ,  H01L2924/014 ,  H01L2924/00014

摘要： A semiconductor package having an internal heat distribution layer and methods of forming the semiconductor package are provided. The semiconductor package can include a first semiconductor device, a second semiconductor device, and an external heat distribution layer. The first semiconductor device can comprise a first semiconductor die and an external surface comprising a top surface, a bottom surface, and a side surface joining the bottom surface to the tope surface. The second semiconductor device can comprise a second semiconductor die and can be stacked on the top surface of the first semiconductor device. The external heat distribution layer can cover an external surface of the second semiconductor device and the side surface of the first semiconductor device. The external heat distribution layer further contacts an internal heat distribution layer on a top surface of the first semiconductor die.

公开(公告)号：US20170294402A1

公开(公告)日：2017-10-12

申请号：US15632686

申请日：2017-06-26

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Zheng-Yi Lim ,  Yi-Wen Wu ,  Tzong-Hann Yang ,  Ming-Che Ho ,  Chung-Shi Liu

IPC分类号： H01L23/00

CPC分类号： H01L24/81 ,  H01L21/56 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49833 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/13016 ,  H01L2224/13017 ,  H01L2224/13018 ,  H01L2224/13023 ,  H01L2224/13124 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13582 ,  H01L2224/13583 ,  H01L2224/13611 ,  H01L2224/13644 ,  H01L2224/13647 ,  H01L2224/13655 ,  H01L2224/13657 ,  H01L2224/13664 ,  H01L2224/16148 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/16501 ,  H01L2224/16505 ,  H01L2224/32135 ,  H01L2224/32141 ,  H01L2224/32145 ,  H01L2224/81085 ,  H01L2224/811 ,  H01L2224/8112 ,  H01L2224/81121 ,  H01L2224/81193 ,  H01L2224/81232 ,  H01L2224/81355 ,  H01L2224/81359 ,  H01L2224/81801 ,  H01L2224/8192 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/1533 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2924/3841 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/01005 ,  H01L2924/01074 ,  H01L2924/01015 ,  H01L2924/06 ,  H01L2924/00

摘要： A method includes aligning a first electrical connector of a first package component to a second electrical connector of a second package component. With the first electrical connector aligned to the second electrical connector, a metal layer is plated on the first and the second electrical connectors. The metal layer bonds the first electrical connector to the second electrical connector.

公开(公告)号：US09418922B2

公开(公告)日：2016-08-16

申请号：US14524443

申请日：2014-10-27

申请人： Amkor Technology, Inc.

发明人： Jong Sik Paek ,  Doo Hyun Park

IPC分类号： H01L23/498 ,  H01L23/00 ,  H01L25/07 ,  H01L25/00 ,  H01L21/56

CPC分类号： H01L23/49816 ,  H01L21/568 ,  H01L23/3128 ,  H01L24/17 ,  H01L24/24 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/81 ,  H01L24/82 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/074 ,  H01L25/50 ,  H01L2224/16237 ,  H01L2224/24101 ,  H01L2224/24146 ,  H01L2224/2612 ,  H01L2224/291 ,  H01L2224/32135 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48227 ,  H01L2224/49 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/81005 ,  H01L2224/81203 ,  H01L2224/82106 ,  H01L2224/83005 ,  H01L2224/85 ,  H01L2224/85005 ,  H01L2224/85203 ,  H01L2224/92125 ,  H01L2224/92225 ,  H01L2224/92244 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06558 ,  H01L2225/06562 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012 ,  H05K3/4661 ,  H01L2224/82 ,  H01L2224/32245 ,  H01L2224/48247

摘要： A semiconductor device with reduced thickness is disclosed and may include forming a back end of line (BEOL) comprising a redistribution layer on a dummy substrate. A first semiconductor die may be bonded to a first surface of the BEOL and a second semiconductor die may be bonded to the first semiconductor die. The first and second semiconductor dies may be electrically coupled to the BEOL. The first and second semiconductor dies and the BEOL may be encapsulated utilizing a first encapsulant. The dummy substrate may be removed thereby exposing a second surface of the BEOL opposite to the first surface. A solder ball may be placed on the exposed second surface of the BEOL. The second semiconductor may be stacked stepwise on the first semiconductor and may be flip-chip bonded. The semiconductor dies may be electrically coupled to the BEOL utilizing a lateral plating layer or conductive wires.

摘要翻译： 公开了一种具有减小厚度的半导体器件，并且可以包括在虚设衬底上形成包括再分配层的线路后端（BEOL）。 第一半导体管芯可以结合到BEOL的第一表面上，并且第二半导体管芯可以结合到第一半导体管芯。 第一和第二半导体管芯可以电耦合到BEOL。 可以利用第一密封剂来封装第一和第二半导体管芯和BEOL。 可以去除虚设衬底，从而暴露与第一表面相对的BEOL的第二表面。 焊球可以放置在BEOL的暴露的第二表面上。 第二半导体可以逐层堆叠在第一半导体上，并且可以倒装芯片接合。 半导体管芯可以使用横向镀层或导电线电耦合到BEOL。

公开(公告)号：US20140071652A1

公开(公告)日：2014-03-13

申请号：US13611076

申请日：2012-09-12

申请人： MICHAEL B. MCSHANE ,  KEVIN J. HESS ,  PERRY H. PELLEY ,  TAB A. STEPHENS

发明人： MICHAEL B. MCSHANE ,  KEVIN J. HESS ,  PERRY H. PELLEY ,  TAB A. STEPHENS

IPC分类号： H05K7/00

CPC分类号： H01L23/48 ,  H01L23/538 ,  H01L24/16 ,  H01L24/24 ,  H01L24/32 ,  H01L24/73 ,  H01L24/82 ,  H01L25/04 ,  H01L25/0657 ,  H01L2224/131 ,  H01L2224/16146 ,  H01L2224/24146 ,  H01L2224/245 ,  H01L2224/2518 ,  H01L2224/32135 ,  H01L2224/73217 ,  H01L2224/73259 ,  H01L2224/8203 ,  H01L2224/82101 ,  H01L2224/83 ,  H01L2224/9202 ,  H01L2224/92144 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/01029 ,  H01L2924/01013 ,  H01L2224/81 ,  H01L2924/014

摘要： An electronic assembly includes a processor die assembly, a first die assembly, and a second die assembly. The first die assembly is positioned on a first side of the processor die assembly. The second die assembly is positioned on a second side of the processor die assembly opposite the first side of the processor die assembly. Through-die vias couple the first and second die assemblies to the processor die assembly.

摘要翻译： 电子组件包括处理器模具组件，第一模具组件和第二模具组件。 第一模具组件定位在处理器模具组件的第一侧上。 第二模具组件位于处理器模具组件的与处理器模具组件的第一侧相对的第二侧。 通孔将第一和第二模具组件耦合到处理器模具组件。

公开(公告)号：US20120007227A1

公开(公告)日：2012-01-12

申请号：US13162846

申请日：2011-06-17

申请人： Yun-Rae CHO ,  Kun-Dae Yeom

发明人： Yun-Rae CHO ,  Kun-Dae Yeom

IPC分类号： H01L25/11 ,  H01L25/07

CPC分类号： H01L25/03 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3121 ,  H01L23/3128 ,  H01L24/05 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/92 ,  H01L24/96 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68368 ,  H01L2221/68381 ,  H01L2224/04042 ,  H01L2224/056 ,  H01L2224/2919 ,  H01L2224/32135 ,  H01L2224/32145 ,  H01L2224/32151 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48177 ,  H01L2224/484 ,  H01L2224/48599 ,  H01L2224/4899 ,  H01L2224/4911 ,  H01L2224/49113 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/83005 ,  H01L2224/85005 ,  H01L2224/92165 ,  H01L2225/06562 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01061 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor package including a protection layer, a plurality of semiconductor chips stacked on the protection layer, an inner encapsulant disposed on the protection layer to surround side surfaces of the semiconductor chips, and a terminal disposed to be buried in an upper portion of the inner encapsulant. Herein, each of the semiconductor chips includes an active surface, an inactive surface opposite to the active surface, and a chip pad disposed on a portion of the active surface, and an upper surface of the terminal is exposed from an upper surface of the inner encapsulant.

摘要翻译： 一种半导体封装，包括保护层，堆叠在保护层上的多个半导体芯片，设置在保护层上以包围半导体芯片的侧表面的内部密封剂，以及被设置成埋入内部的上部的端子 密封剂。 这里，每个半导体芯片包括有源表面，与有源表面相对的无效表面和设置在有源表面的一部分上的芯片焊盘，并且端子的上表面从内表面的上表面露出 密封剂。