公开(公告)号：US20230170267A1

公开(公告)日：2023-06-01

申请号：US18073108

申请日：2022-12-01

申请人： JCET MANAGEMENT CO., LTD.

发明人： CHENG YANG

IPC分类号： H01L23/13 ,  H01L25/065 ,  H01L23/498 ,  H01L23/367 ,  H01L23/373 ,  H01L23/00 ,  H01L21/48 ,  H01L25/00

CPC分类号： H01L23/13 ,  H01L25/0657 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/3675 ,  H01L23/3735 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/4882 ,  H01L25/50 ,  H01L23/49838 ,  H01L2924/15151 ,  H01L2924/152 ,  H01L2224/73253 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32245 ,  H01L2225/06517 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06589 ,  H01L2225/06568

摘要： The present invention provides a packaging structure and a manufacturing method thereof. The packaging structure includes a first substrate, a first chip, a second chip, a first heat conductor and a second heat conductor, wherein the first substrate includes a cavity; the first chip is embedded in the cavity and includes a first connecting surface and a first heat-conducting surface that face away from each other; the second chip is disposed on a side of the first connecting surface and electrically connected to the first chip, a side of the second chip distal from the first chip includes a second heat-conducting surface on a side; and the first heat conductor is connected to the first heat-conducting surface, and the second heat conductor is connected to the second heat-conducting surface. The first substrate includes a third connecting surface that is flush with the first connecting surface.

公开(公告)号：US09431371B2

公开(公告)日：2016-08-30

申请号：US14701388

申请日：2015-04-30

申请人： BROADCOM CORPORATION

发明人： Sampath K. Karikalan ,  Sam Ziqun Zhao ,  Kevin Kunzhong Hu ,  Rezaur Rahman Khan ,  Pieter Vorenkamp ,  Xiangdong Chen

IPC分类号： H01L25/00 ,  H01L25/065 ,  H01L23/00

CPC分类号： H01L25/0655 ,  H01L23/48 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/538 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/80 ,  H01L24/82 ,  H01L25/0652 ,  H01L2224/0401 ,  H01L2224/05541 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73203 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/96 ,  H01L2924/00014 ,  H01L2924/15192 ,  H01L2924/152 ,  H01L2924/1532 ,  H01L2924/30105 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： There are disclosed herein various implementations of semiconductor packages including a bridge interposer. One exemplary implementation includes a first active die having a first portion situated over the bridge interposer, and a second portion not situated over the bridge interposer. The semiconductor package also includes a second active die having a first portion situated over the bridge interposer, and a second portion not situated over the bridge interposer. The second portion of the first active die and the second portion of the second active die include solder balls mounted on a package substrate, and are configured to communicate electrical signals to the package substrate utilizing the solder balls and without utilizing through-semiconductor vias (TSVs).

公开(公告)号：US09349707B1

公开(公告)日：2016-05-24

申请号：US14609896

申请日：2015-01-30

申请人： Invensas Corporation

发明人： Zhuowen Sun ,  Yong Chen ,  Kyong-Mo Bang

IPC分类号： H01L23/02 ,  H01L25/065 ,  H01L25/00 ,  H01L23/00 ,  H01L23/498 ,  H01L21/48

CPC分类号： H01L25/0652 ,  H01L21/486 ,  H01L23/13 ,  H01L23/34 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/11 ,  H01L24/17 ,  H01L24/43 ,  H01L24/48 ,  H01L24/49 ,  H01L24/81 ,  H01L24/85 ,  H01L25/50 ,  H01L2224/13023 ,  H01L2224/13025 ,  H01L2224/16057 ,  H01L2224/16137 ,  H01L2224/16146 ,  H01L2224/16165 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/4502 ,  H01L2224/48138 ,  H01L2224/48148 ,  H01L2224/48165 ,  H01L2224/48235 ,  H01L2224/4824 ,  H01L2224/49174 ,  H01L2224/49177 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/1434 ,  H01L2924/1511 ,  H01L2924/152 ,  H01L2924/15311 ,  H01L2924/1533 ,  H01L2924/3701 ,  H01L2224/45099

摘要： An apparatus relates generally to a microelectronic assembly. In this apparatus, a first substrate and a second substrate each have opposing surfaces. Contact arrangements are disposed on a surface of the first substrate, including: first contacts disposed as a ring to provide a first array of the contact arrangements on such surface; and second contacts disposed interior to the ring of the first contacts to provide a second array of the contact arrangements on the first surface. The first contacts and the second contacts are for interconnection with first microelectronic dies and second microelectronic dies. The second microelectronic dies are disposed below the first microelectronic dies in same a package as the first microelectronic dies. The first microelectronic dies and the second microelectronic dies include at least two ranks thereof for commonly sharing the first contacts and the second contacts among the first microelectronic dies and the second microelectronic dies.

摘要翻译： 装置一般涉及微电子组件。 在该装置中，第一基板和第二基板各自具有相对的表面。 接触装置设置在第一基板的表面上，包括：作为环设置的第一触点，以在该表面上提供接触装置的第一阵列; 以及第二触点，其设置在第一触头的环的内部，以在第一表面上提供接触装置的第二阵列。 第一触点和第二触点用于与第一微电子管芯和第二微电子管芯互连。 第二微电子管芯以与第一微电子管芯相同的封装设置在第一微电子管芯的下方。 第一微电子管芯和第二微电子管芯包括至少两个等级，用于共同共享第一微触点和第一微电子管芯与第二微电子管芯之间的第二触点。

公开(公告)号：US20160126695A1

公开(公告)日：2016-05-05

申请号：US14531291

申请日：2014-11-03

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Jeffrey P. GAMBINO ,  Richard S. GRAF ,  Robert K. LEIDY ,  Jeffrey C. MALING

IPC分类号： H01S5/022

CPC分类号： H01S5/02272 ,  H01L23/4825 ,  H01L24/06 ,  H01L24/17 ,  H01L2224/05573 ,  H01L2224/05582 ,  H01L2224/0601 ,  H01L2224/1403 ,  H01L2224/1703 ,  H01L2924/12042 ,  H01L2924/152

摘要： A dual bond pad structure for a wafer with laser die attachment and methods of manufacture are disclosed. The method includes forming a bonding layer on a surface of a substrate. The method further includes forming solder bumps on the bonding layer. The method further includes patterning the bonding layer to form bonding pads some of which comprise the solder bumps thereon. The method further includes attaching a laser diode to selected bonding pads using solder connections formed on the laser diode. The method further includes attaching an interposer substrate to the solder bumps formed on the bonding pads.

摘要翻译： 公开了一种用于具有激光芯片附件的晶片的双键焊盘结构和制造方法。 该方法包括在基板的表面上形成接合层。 该方法还包括在接合层上形成焊料凸块。 该方法还包括图案化结合层以形成其中包括其上的焊料凸点的焊盘。 该方法还包括使用形成在激光二极管上的焊料连接将激光二极管附接到选定的焊盘。 该方法还包括将内插衬底附接到形成在接合焊盘上的焊料凸块。

公开(公告)号：US20150262841A1

公开(公告)日：2015-09-17

申请号：US14568603

申请日：2014-12-12

申请人： Samsung Electronics Co., Ltd.

发明人： Hee Jeong KIM ,  Yong Kwan LEE

IPC分类号： H01L21/48 ,  H05K3/06 ,  H01L25/00 ,  H01L25/065 ,  H01L21/52 ,  H01L23/00

CPC分类号： H05K3/06 ,  H01L21/486 ,  H01L21/52 ,  H01L23/13 ,  H01L23/145 ,  H01L23/3128 ,  H01L23/49827 ,  H01L24/16 ,  H01L24/32 ,  H01L24/43 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/85 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/29036 ,  H01L2224/32135 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/451 ,  H01L2224/48106 ,  H01L2224/48228 ,  H01L2224/48235 ,  H01L2224/49176 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06548 ,  H01L2225/06568 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/15153 ,  H01L2924/15156 ,  H01L2924/152 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15331 ,  H05K1/144 ,  H05K1/183 ,  H05K3/4697 ,  H05K2201/041 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2224/48227 ,  H01L2924/00012

摘要： A method of manufacturing a circuit board may include: preparing a circuit board body including an insulating layer having a first surface and a second surface opposite to the first surface and a first conductive thin film layer disposed on the first surface of the insulating layer and having a convex portion which is disposed on a first surface of the first conductive thin film layer and is embedded in the insulating layer; removing the convex portion to form a cavity corresponding to the convex portion in the insulating layer; and forming one or more first wiring patterns on the first surface of the insulating layer by removing first portions of the first conductive thin film layer. The one or more first wiring patterns correspond to second portions of the first conductive thin film layer not removed.

摘要翻译： 制造电路板的方法可以包括：制备电路板主体，其包括具有第一表面和与第一表面相对的第二表面的绝缘层，以及设置在绝缘层的第一表面上的第一导电薄膜层，并且具有 凸部，其设置在所述第一导电性薄膜层的第一表面上并嵌入所述绝缘层中; 去除所述凸部以形成与所述绝缘层中的所述凸部对应的空腔; 以及通过去除第一导电薄膜层的第一部分，在绝缘层的第一表面上形成一个或多个第一布线图案。 一个或多个第一布线图案对应于未被去除的第一导电薄膜层的第二部分。

公开(公告)号：US20230282626A1

公开(公告)日：2023-09-07

申请号：US18163417

申请日：2023-02-02

申请人： MEDIATEK INC.

发明人： Tai-Yu CHEN ,  Bo-Jiun YANG ,  Tsung-Yu PAN ,  Yin-Fa CHEN ,  Ta-Jen YU ,  Bo-Hao MA ,  Wen-Sung HSU ,  Yao-Pang HSU

IPC分类号： H01L25/10 ,  H01L23/498 ,  H01L23/00 ,  H01L23/14

CPC分类号： H01L25/105 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/49838 ,  H01L24/16 ,  H01L23/147 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2224/16227 ,  H01L2924/15311 ,  H01L2924/182 ,  H01L2924/157 ,  H01L2924/15787 ,  H01L2924/1511 ,  H01L2924/152

摘要： A high-bandwidth package-on-package (HBPoP) structure includes a first package structure and a second package structure disposed over the first package structure. The first package structure includes a first package substrate, a semiconductor die, an interposer, and a molding material. The first package substrate is formed of a silicon and/or ceramic material. The semiconductor die is disposed over the first package substrate. The interposer is disposed over the semiconductor die and is formed of a silicon and/or ceramic material. The molding material is disposed between the first package substrate and the interposer and surrounds the semiconductor die.

公开(公告)号：US20180096903A1

公开(公告)日：2018-04-05

申请号：US15832938

申请日：2017-12-06

申请人： Samsung Electronics Co., Ltd.

发明人： Younghoon Sohn ,  Jinsung Kim ,  Yusin Yang ,  Chungsam Jun

IPC分类号： H01L21/66 ,  H01L23/00 ,  H01L21/027 ,  H01L21/311 ,  H01L21/768 ,  H01L21/56 ,  H01L21/67 ,  H01L21/683 ,  H01L21/48 ,  H01L21/02

CPC分类号： H01L22/12 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02271 ,  H01L21/0274 ,  H01L21/31144 ,  H01L21/4846 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/67259 ,  H01L21/6835 ,  H01L21/76802 ,  H01L21/76895 ,  H01L22/20 ,  H01L23/3128 ,  H01L24/06 ,  H01L24/11 ,  H01L2221/68345 ,  H01L2224/02311 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13024 ,  H01L2224/14131 ,  H01L2224/96 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/15153 ,  H01L2924/152 ,  H01L2924/15747

摘要： A method of fabricating a package includes providing a mold substrate supporting dies in cavities of a fan-out substrate, detecting positions of the dies with respect to the fan-out substrate, and forming interconnection lines. At least one of the interconnection lines includes a first portion extending from the fan-out substrate to a target position on the cavity disposed between the fan-out substrate and one of the dies the one of the dies disposed at a detected position different from the target position, and a second portion extending from the one die to the fan-out substrate.

公开(公告)号：US20170181288A1

公开(公告)日：2017-06-22

申请号：US15386172

申请日：2016-12-21

申请人： Murata Manufacturing Co., Ltd.

发明人： Yasuo FUJII

IPC分类号： H05K1/18 ,  H01G4/005 ,  H01L23/498 ,  H05K1/11 ,  H01L23/00 ,  H01G4/30 ,  H01G4/248

CPC分类号： H05K1/185 ,  H01G2/06 ,  H01G4/005 ,  H01G4/232 ,  H01G4/248 ,  H01G4/30 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/17 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2924/152 ,  H01L2924/19041 ,  H01L2924/19102 ,  H05K1/115 ,  H05K1/181 ,  H05K2201/10015

摘要： In a capacitor, a width in a length direction of a first portion of a third outer electrode, which is a portion located on a first side surface, is greater than a width in a length direction of a second portion of the third outer electrode, which is a portion located on a first main surface. The first portion of the third outer electrode does not extend to first and second end surfaces.

公开(公告)号：US20160049345A1

公开(公告)日：2016-02-18

申请号：US14925159

申请日：2015-10-28

申请人： International Business Machines Corporation

发明人： Peter J. Brofman ,  Marie-Claude Paquet ,  Julien Sylvestre

IPC分类号： H01L23/31 ,  H01L23/00 ,  H01L25/065 ,  H01L23/498

CPC分类号： H01L23/3142 ,  H01L21/563 ,  H01L23/49838 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/27 ,  H01L24/29 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/131 ,  H01L2224/14131 ,  H01L2224/16145 ,  H01L2224/16148 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/2732 ,  H01L2224/2755 ,  H01L2224/29036 ,  H01L2224/2919 ,  H01L2224/3201 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81801 ,  H01L2224/81815 ,  H01L2224/83102 ,  H01L2224/83191 ,  H01L2224/83947 ,  H01L2224/83951 ,  H01L2224/83986 ,  H01L2224/92125 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/152 ,  H01L2924/15311 ,  H01L2924/182 ,  H01L2924/183 ,  H01L2924/351 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014

摘要： The present invention relates generally to flip chip technology and more particularly, to a method and structure for reducing internal packaging stresses, improving adhesion properties, and reducing thermal resistance in flip chip packages by using more than one underfill material deposited in different regions of the flip chip interface. According to one embodiment, a method of forming a first underfill in an interior region of an interface such that a periphery region of the interface remains open, and forming a second underfill in the periphery region is disclosed.

公开(公告)号：US20150255312A1

公开(公告)日：2015-09-10

申请号：US14197280

申请日：2014-03-05

申请人： International Business Machines Corporation

发明人： Peter J. Brofman ,  Marie-Claude Paquet ,  Julien Sylvestre

IPC分类号： H01L21/56 ,  H01L25/10 ,  H01L23/00

CPC分类号： H01L23/3142 ,  H01L21/563 ,  H01L23/49838 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/27 ,  H01L24/29 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/131 ,  H01L2224/14131 ,  H01L2224/16145 ,  H01L2224/16148 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/2732 ,  H01L2224/2755 ,  H01L2224/29036 ,  H01L2224/2919 ,  H01L2224/3201 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81801 ,  H01L2224/81815 ,  H01L2224/83102 ,  H01L2224/83191 ,  H01L2224/83947 ,  H01L2224/83951 ,  H01L2224/83986 ,  H01L2224/92125 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/152 ,  H01L2924/15311 ,  H01L2924/182 ,  H01L2924/183 ,  H01L2924/351 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014

摘要： The present invention relates generally to flip chip technology and more particularly, to a method and structure for reducing internal packaging stresses, improving adhesion properties, and reducing thermal resistance in flip chip packages by using more than one underfill material deposited in different regions of the flip chip interface. According to one embodiment, a method of forming a first underfill in an interior region of an interface such that a periphery region of the interface remains open, and forming a second underfill in the periphery region is disclosed.

摘要翻译： 本发明一般涉及倒装芯片技术，更具体地说，涉及一种用于减少内部封装应力，改善粘合性能以及通过使用沉积在翻盖的不同区域中的多于一个底部填充材料来降低倒装芯片封装中的热阻的方法和结构 芯片接口。 根据一个实施方案，公开了一种在界面的内部区域中形成第一底部填充物的方法，使得界面的外围区域保持开放，并且在周边区域中形成第二底部填充物。