公开(公告)号：US12107082B2

公开(公告)日：2024-10-01

申请号：US18368424

申请日：2023-09-14

Applicant: Intel Corporation

Inventor： Russell K. Mortensen ,  Robert M. Nickerson ,  Nicholas R. Watts

IPC: H01L21/00 ,  H01L21/44 ,  H01L21/48 ,  H01L21/50 ,  H01L21/56 ,  H01L21/60 ,  H01L23/00 ,  H01L23/02 ,  H01L23/28 ,  H01L23/31 ,  H01L23/48 ,  H01L23/488 ,  H01L23/498 ,  H01L23/52 ,  H01L23/538 ,  H01L23/552 ,  H01L25/00 ,  H01L25/065 ,  H01L25/10 ,  H01L25/11 ,  H01L25/18 ,  H05K1/02 ,  H05K1/11 ,  H05K3/40

CPC classification number: H01L25/18 ,  H01L21/4846 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L24/03 ,  H01L24/09 ,  H01L24/11 ,  H01L24/17 ,  H01L24/43 ,  H01L24/49 ,  H01L24/73 ,  H01L24/81 ,  H01L24/85 ,  H01L24/89 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H05K1/113 ,  H05K3/4038 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/08238 ,  H01L2224/13025 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48227 ,  H01L2224/48245 ,  H01L2224/48472 ,  H01L2224/73204 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06572 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/00014 ,  H01L2924/143 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1511 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/381 ,  Y10T29/49124 ,  H01L2224/73204 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2924/00012 ,  H01L2924/15311 ,  H01L2224/73204 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2924/00012 ,  H01L2224/73265 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2924/00 ,  H01L2924/15311 ,  H01L2224/73265 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2924/00 ,  H01L2224/73265 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2224/05552 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2924/00014 ,  H01L2224/45099 ,  H01L2924/00014 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/48472 ,  H01L2224/48227 ,  H01L2924/00

Abstract: An offset interposer includes a land side including land-side ball-grid array (BGA) and a package-on-package (POP) side including a POP-side BGA. The land-side BGA includes two adjacent, spaced-apart land-side pads, and the POP-side BGA includes two adjacent, spaced-apart POP-side pads that are coupled to the respective two land-side BGA pads through the offset interposer. The land-side BGA is configured to interface with a first-level interconnect. The POP-side BGA is configured to interface with a POP substrate. Each of the two land-side pads has a different footprint than the respective two POP-side pads.

公开(公告)号：US11978730B2

公开(公告)日：2024-05-07

申请号：US17587664

申请日：2022-01-28

Applicant: Intel Corporation

Inventor： Russell K. Mortensen ,  Robert M. Nickerson ,  Nicholas R. Watts

IPC: H01L21/00 ,  H01L21/44 ,  H01L21/48 ,  H01L21/50 ,  H01L21/56 ,  H01L21/58 ,  H01L21/60 ,  H01L23/00 ,  H01L23/02 ,  H01L23/13 ,  H01L23/28 ,  H01L23/31 ,  H01L23/34 ,  H01L23/44 ,  H01L23/48 ,  H01L23/488 ,  H01L23/498 ,  H01L23/50 ,  H01L23/52 ,  H01L23/538 ,  H01L23/552 ,  H01L23/66 ,  H01L25/00 ,  H01L25/065 ,  H01L25/10 ,  H01L25/11 ,  H01L25/16 ,  H01L25/18 ,  H05K1/11 ,  H05K3/40

CPC classification number: H01L25/18 ,  H01L21/4846 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L24/03 ,  H01L24/09 ,  H01L24/11 ,  H01L24/17 ,  H01L24/43 ,  H01L24/49 ,  H01L24/73 ,  H01L24/81 ,  H01L24/85 ,  H01L24/89 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H05K1/113 ,  H05K3/4038 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/08238 ,  H01L2224/13025 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48227 ,  H01L2224/48245 ,  H01L2224/48472 ,  H01L2224/73204 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06572 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/00014 ,  H01L2924/143 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1511 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/381 ,  Y10T29/49124 ,  H01L2224/73204 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2924/00012 ,  H01L2924/15311 ,  H01L2224/73204 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2924/00012 ,  H01L2224/73265 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2924/00 ,  H01L2924/15311 ,  H01L2224/73265 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2924/00 ,  H01L2224/73265 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2224/05552 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2924/00014 ,  H01L2224/45099 ,  H01L2924/00014 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/48472 ,  H01L2224/48227 ,  H01L2924/00

Abstract: An offset interposer includes a land side including land-side ball-grid array (BGA) and a package-on-package (POP) side including a POP-side BGA. The land-side BGA includes two adjacent, spaced-apart land-side pads, and the POP-side BGA includes two adjacent, spaced-apart POP-side pads that are coupled to the respective two land-side BGA pads through the offset interposer. The land-side BGA is configured to interface with a first-level interconnect. The POP-side BGA is configured to interface with a POP substrate. Each of the two land-side pads has a different footprint than the respective two POP-side pads.

公开(公告)号：US11862600B2

公开(公告)日：2024-01-02

申请号：US17491647

申请日：2021-10-01

Applicant: Infineon Technologies AG

Inventor： Thorsten Scharf ,  Alexander Heinrich ,  Steffen Jordan

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/00 ,  H01L21/56 ,  H01L23/498

CPC classification number: H01L24/80 ,  H01L21/565 ,  H01L23/4985 ,  H01L2224/80357 ,  H01L2224/83385 ,  H01L2924/1511 ,  H01L2924/15724 ,  H01L2924/15738

Abstract: A method of forming a chip package is provided. The method includes providing a malleable carrier with a layer of an electrically conductive material formed thereon, and positive fitting the malleable carrier to a chip to at least partially enclose the chip with the malleable carrier. The layer at least partially physically contacts the chip, such that the layer electrically contacts a chip contact of the chip. The layer forms a redistribution layer.

公开(公告)号：US20230215816A1

公开(公告)日：2023-07-06

申请号：US17566575

申请日：2021-12-30

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Cheng-Yuan KUNG ,  Hsu-Chiang SHIH ,  Hung-Yi LIN ,  Chien-Mei HUANG

IPC: H01L23/00 ,  H01L23/498 ,  H01L25/065 ,  H01L23/538

CPC classification number: H01L23/562 ,  H01L23/5383 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/16 ,  H01L25/0655 ,  H01L2224/16227 ,  H01L2924/1511 ,  H01L2924/3512

Abstract: A package structure includes an encapsulant, a patterned circuit structure, at least one electronic component and a shrinkage modifier. The patterned circuit structure is disposed on the encapsulant and includes a pad. The electronic component is disposed on the patterned circuit structure, and includes a bump electrically connected to the pad. The shrinkage modifier is encapsulated in the encapsulant and configured to reduce a relative displacement between the bump and the pad along a horizontal direction in an environment of temperature variation.

公开(公告)号：US20170287838A1

公开(公告)日：2017-10-05

申请号：US15089509

申请日：2016-04-02

Applicant: Intel Corporation

Inventor： Srinivas V. Pietambaram ,  Rahul N. Manepalli

IPC: H01L23/538 ,  H01L23/00 ,  H01L25/065 ,  H01L23/498 ,  H01L21/48

CPC classification number: H01L23/5381 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/13 ,  H01L24/17 ,  H01L25/0655 ,  H01L2224/131 ,  H01L2224/16113 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/92125 ,  H01L2924/05432 ,  H01L2924/05442 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/1511 ,  H01L2924/15192 ,  H01L2924/15747 ,  H01L2924/1579 ,  H01L2924/181 ,  H01L2924/00

Abstract: Electrical interconnect bridge technology is disclosed. An electrical interconnect bridge can include a bridge substrate formed of a mold compound material. The electrical interconnect bridge can also include a plurality of routing layers within the bridge substrate, each routing layer having a plurality of fine line and space (FLS) traces. In addition, the electrical interconnect bridge can include a via extending through the substrate and electrically coupling at least one of the FLS traces in one of the routing layers to at least one of the FLS traces in another of the routing layers.

公开(公告)号：US09780017B2

公开(公告)日：2017-10-03

申请号：US15346822

申请日：2016-11-09

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Benjamin Stassen Cook ,  Juan Alejandro Herbsommer ,  Yong Lin ,  Rongwei Zhang ,  Abram Castro ,  Matthew David Romig

IPC: H01L23/49 ,  H01L23/495 ,  H01L21/288 ,  H01L21/48 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L23/4952 ,  H01L21/2885 ,  H01L21/4821 ,  H01L21/4825 ,  H01L21/4867 ,  H01L23/49513 ,  H01L23/49541 ,  H01L23/49572 ,  H01L23/49582 ,  H01L23/49586 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/49883 ,  H01L24/05 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/04042 ,  H01L2224/0612 ,  H01L2224/16245 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48464 ,  H01L2224/73265 ,  H01L2224/75 ,  H01L2224/83192 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06555 ,  H01L2924/00014 ,  H01L2924/13055 ,  H01L2924/14 ,  H01L2924/1511 ,  H01L2924/1711 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/0665

Abstract: A method of lead frame surface modification includes providing at least one pre-fabricated metal lead frame or package substrate (substrate) unit including a base metal having a die pad and a plurality of contact regions surrounding the die pad. An ink including a material that is a solid or a precursor for a solid that forms a solid upon a curing step or a sintering step that removes a liquid carrier is additively deposited including onto at least one of (i) a region of the die pad and (ii) at one region of at least a first of the contact regions (first contact region). The ink is sintered or cured to remove the liquid carrier so that a substantially solid ink residue remains.

公开(公告)号：US20170236794A1

公开(公告)日：2017-08-17

申请号：US15584961

申请日：2017-05-02

Applicant: Invensas Corporation

Inventor： Liang Wang ,  Rajesh Katkar ,  Hong Shen

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/34

CPC classification number: H01L24/09 ,  B81B7/008 ,  B81B2207/07 ,  B81C1/0023 ,  H01L21/565 ,  H01L21/76877 ,  H01L23/3107 ,  H01L23/3157 ,  H01L23/34 ,  H01L23/367 ,  H01L23/481 ,  H01L23/49838 ,  H01L23/5389 ,  H01L24/06 ,  H01L24/17 ,  H01L24/19 ,  H01L24/20 ,  H01L24/33 ,  H01L24/48 ,  H01L24/49 ,  H01L24/89 ,  H01L24/96 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/10 ,  H01L25/105 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/06181 ,  H01L2224/08225 ,  H01L2224/09181 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/33517 ,  H01L2224/48135 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73207 ,  H01L2224/73209 ,  H01L2224/73253 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2224/80001 ,  H01L2224/81005 ,  H01L2224/92124 ,  H01L2224/92133 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06548 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/1511 ,  H01L2924/15153 ,  H01L2924/15192 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/32225 ,  H01L2924/00012 ,  H01L2224/05599 ,  H01L2224/85399

Abstract: In a multi-chip module (MCM), a “super” chip (110N) is attached to multiple “plain” chips (110F′ “super” and “plain” chips can be any chips). The super chip is positioned above the wiring board (WB) but below at least some of plain chips (110F). The plain chips overlap the super chip. Further, the plain chips' low speed IOs can be connected to the WB by long direct connections such as bond wires (e.g. BVAs) or solder stacks; such connections can be placed side by side with the super chip. Such connections can be long, so the super chip is not required to be thin. Also, if through-substrate vias (TSVs) are omitted, the manufacturing yield is high and the manufacturing cost is low. Other structures are provided that combine the short and long direct connections to obtain desired physical and electrical properties.

公开(公告)号：US09524926B2

公开(公告)日：2016-12-20

申请号：US14848975

申请日：2015-09-09

Applicant: Texas Instruments Incorporated

Inventor： Benjamin Stassen Cook ,  Juan Alejandro Herbsommer ,  Yong Lin ,  Rongwei Zhang ,  Abram Castro ,  Matthew David Romig

IPC: H01L23/49 ,  H01L23/495 ,  H01L21/288 ,  H01L21/48 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L23/4952 ,  H01L21/2885 ,  H01L21/4821 ,  H01L21/4825 ,  H01L21/4867 ,  H01L23/49513 ,  H01L23/49541 ,  H01L23/49572 ,  H01L23/49582 ,  H01L23/49586 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/49883 ,  H01L24/05 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/04042 ,  H01L2224/0612 ,  H01L2224/16245 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48464 ,  H01L2224/73265 ,  H01L2224/75 ,  H01L2224/83192 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06555 ,  H01L2924/00014 ,  H01L2924/13055 ,  H01L2924/14 ,  H01L2924/1511 ,  H01L2924/1711 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/0665

Abstract: A method of lead frame surface modification includes providing at least one pre-fabricated metal lead frame or package substrate (substrate) unit including a base metal having a die pad and a plurality of contact regions surrounding the die pad. An ink including a material that is a solid or a precursor for a solid that forms a solid upon a curing step or a sintering step that removes a liquid carrier is additively deposited including onto at least one of (i) a region of the die pad and (ii) at one region of at least a first of the contact regions (first contact region). The ink is sintered or cured to remove the liquid carrier so that a substantially solid ink residue remains.

Abstract translation: 引线框架表面改性的方法包括提供至少一个预制金属引线框架或封装基板（基板）单元，其包括具有管芯焊盘和围绕管芯焊盘的多个接触区域的母材。 包括在固化步骤上形成固体的固体的材料或去除液体载体的烧结步骤的材料的油墨被加成沉积，其包括至少一个（i）芯片垫的区域 和（ii）在至少第一接触区域（第一接触区域）的一个区域。 油墨被烧结或固化以除去液体载体，使得残留基本上固体的油墨残余物。

公开(公告)号：US09418929B1

公开(公告)日：2016-08-16

申请号：US14692747

申请日：2015-04-22

Applicant: Boon Yew Low ,  Weng Hoong Chan

Inventor： Boon Yew Low ,  Weng Hoong Chan

IPC: H01L23/055 ,  H01L23/48 ,  H01L23/498 ,  H01L23/00 ,  H01L23/532 ,  H01L23/31 ,  H01L25/065 ,  H01L21/768

CPC classification number: H01L23/49838 ,  H01L23/14 ,  H01L23/145 ,  H01L23/4985 ,  H01L23/49877 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L25/0655 ,  H01L2221/1094 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/1511 ,  H01L2924/15153 ,  H01L2924/15192 ,  H01L2924/1531 ,  H01L2924/181 ,  H01L2224/45099

Abstract: A packaged integrated circuit (IC) device includes a flexible substrate having contact pads, an IC die mounted on the substrate and electrically connected to the contact pads, and conductive threads sewn into the substrate. The conductive threads have proximal ends electrically connected to corresponding ones of the contact pads with conductive bumps. The conductive threads eliminate the need for a complicated multi-layer substrate structure for interconnect fan-out so the substrate may be formed of a variety of materials such as cloth or paper.

Abstract translation: 封装集成电路（IC）装置包括具有接触焊盘的柔性基板，安装在基板上并电连接到接触焊盘的IC管芯，以及缝合到基板中的导电线。 导电线具有电连接到具有导电凸块的相应接触垫的近端。 导电丝不需要用于互连扇出的复杂的多层衬底结构，因此衬底可以由各种材料如布或纸形成。

公开(公告)号：US20160204051A1

公开(公告)日：2016-07-14

申请号：US14596079

申请日：2015-01-13

Applicant: Winbond Electronics Corp.

Inventor： Yu-Ting CHENG ,  Yu-Min FU

IPC: H01L23/498 ,  H01L23/00

CPC classification number: H01L23/4985 ,  H01L23/13 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/562 ,  H01L24/09 ,  H01L24/16 ,  H01L24/17 ,  H01L2224/08225 ,  H01L2224/08238 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/1415 ,  H01L2224/16227 ,  H01L2924/1511 ,  H01L2924/15151 ,  H01L2924/15159 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A flexible microsystem structure is provided. The flexible microsystem structure includes a flexible substrate; and a chip disposed over the flexible substrate, wherein the chip is bonded to the flexible substrate by a plurality of bonding elements disposed over the flexible substrate; wherein the flexible substrate has at least one trench disposed under the chip and disposed along at least one side of at least one of the bonding elements.

Abstract translation: 提供了灵活的微系统结构。 灵活的微系统结构包括柔性基板; 以及设置在所述柔性基板上的芯片，其中所述芯片通过设置在所述柔性基板上的多个接合元件接合到所述柔性基板; 其中所述柔性基底具有设置在所述芯片下方的至少一个沟槽，并且沿至少一个所述结合元件的至少一侧设置。