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    Multi-chip modules formed using wafer-level processing of a reconstituted wafer
    2.
    发明授权
    Multi-chip modules formed using wafer-level processing of a reconstituted wafer 有权

    公开(公告)号：US10546834B2

    公开(公告)日：2020-01-28

    申请号：US16246863

    申请日：2019-01-14

    申请人： Invensas Corporation

    发明人： Liang Wang ,  Rajesh Katkar

    IPC分类号： H01L21/56 ,  H01L25/065 ,  H01L23/31 ,  H01L25/00 ,  H01L21/768 ,  H01L23/00

    摘要： Apparatuses and methods are described. This apparatus includes a bridge die having first contacts on a die surface being in a molding layer of a reconstituted wafer. The reconstituted wafer has a wafer surface including a layer surface of the molding layer and the die surface. A redistribution layer on the wafer surface includes electrically conductive and dielectric layers to provide conductive routing and conductors. The conductors extend away from the die surface and are respectively coupled to the first contacts at bottom ends thereof. At least second and third IC dies respectively having second contacts on corresponding die surfaces thereof are interconnected to the bridge die and the redistribution layer. A first portion of the second contacts are interconnected to top ends of the conductors opposite the bottom ends thereof in part for alignment of the at least second and third IC dies to the bridge die.

    HIGH YIELD SUBSTRATE ASSEMBLY
    3.
    发明申请
    HIGH YIELD SUBSTRATE ASSEMBLY 审中-公开

    公开(公告)号：US20190341361A1

    公开(公告)日：2019-11-07

    申请号：US16514104

    申请日：2019-07-17

    申请人： Invensas Corporation

    发明人： Liang Wang ,  Ilyas Mohammed ,  Masud Beroz

    IPC分类号： H01L23/00 ,  H01L21/02 ,  H01L21/683 ,  H01L23/544 ,  H01L25/00 ,  H01L33/00 ,  H01L27/02

    摘要： High yield substrate assembly. In accordance with a first method embodiment, a plurality of piggyback substrates are attached to a carrier substrate. The edges of the plurality of the piggyback substrates are bonded to one another. The plurality of piggyback substrates are removed from the carrier substrate to form a substrate assembly. The substrate assembly is processed to produce a plurality of integrated circuit devices on the substrate assembly. The processing may use manufacturing equipment designed to process wafers larger than individual instances of the plurality of piggyback substrates.

    Anchoring structure of fine pitch bva
    4.
    发明授权
    Anchoring structure of fine pitch bva 有权

    公开(公告)号：US10332854B2

    公开(公告)日：2019-06-25

    申请号：US15332533

    申请日：2016-10-24

    申请人： Invensas Corporation

    发明人： Rajesh Katkar ,  Gabriel Z. Guevara ,  Xuan Li ,  Cyprian Emeka Uzoh ,  Guilian Gao ,  Liang Wang

    IPC分类号： H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L25/10 ,  H01L25/00

    摘要： A microelectronic package can include a substrate having a first surface and a second surface opposite therefrom, the substrate having a first conductive element at the first surface, and a plurality of wire bonds, each of the wire bonds having a base electrically connected to a corresponding one of the first conductive elements and having a tip remote from the base, each wire bond having edge surfaces extending from the tip toward the base. The microelectronic package can also include an encapsulation having a major surface facing away from the first surface of the substrate, the encapsulation having a recess extending from the major surface in a direction toward the first surface of the substrate, the tip of a first one of the wire bonds being disposed within the recess, and an electrically conductive layer overlying an inner surface of the encapsulation exposed within the recess, the electrically conductive layer overlying and electrically connected with the tip of the first one of the wire bonds.

    HYBRID 3D/2.5D INTERPOSER
    5.
    发明申请
    HYBRID 3D/2.5D INTERPOSER 审中-公开

    公开(公告)号：US20190096849A1

    公开(公告)日：2019-03-28

    申请号：US16197686

    申请日：2018-11-21

    申请人： Invensas Corporation

    发明人： Charles G. Woychik ,  Cyprian Emeka Uzoh ,  Sangil Lee ,  Liang Wang ,  Guilian Gao

    IPC分类号： H01L25/065 ,  H01L25/00 ,  H01L21/48 ,  H01L23/00 ,  H01L23/31

    摘要： Representative implementations of devices and techniques provide a hybrid interposer for 3D or 2.5D package arrangements. A quantity of pockets is formed on a surface of a carrier in a predetermined pattern. The pockets are filled with a reflowable conductive material. Chip dice are coupled to the interposer carrier by fixing terminals of the dice into the pockets. The carrier may include topside and backside redistribution layers to provide fanout for the chip dice, for coupling the interposer to another carrier, board, etc. having a pitch greater than that of the chip dice.