公开(公告)号：US12080618B2

公开(公告)日：2024-09-03

申请号：US17583946

申请日：2022-01-25

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Yu-Lung Huang ,  Kuo-Hua Yu ,  Chang-Fu Lin

IPC: H01L23/48 ,  H01L23/367 ,  H01L23/00

CPC classification number: H01L23/3675 ,  H01L24/29 ,  H01L24/32 ,  H01L2224/29109 ,  H01L2224/2919 ,  H01L2224/29191 ,  H01L2224/2929 ,  H01L2224/29291 ,  H01L2224/293 ,  H01L2224/29393 ,  H01L2224/32221 ,  H01L2924/0635

Abstract: A heat dissipation structure is provided and includes a heat dissipation body and an adjustment channel. A carrying area and an active area adjacent to the carrying area are defined on a surface of the heat dissipation body, the carrying area is used for applying a first heat dissipation material thereonto, and the adjustment channel is formed in the active area, where one end of the adjustment channel communicates with the outside of the heat dissipation structure, and the other end communicates with the carrying area. Therefore, when the heat dissipation body is coupled to the electronic component by the first heat dissipation material, the adjustment channel can adjust a volume of the first heat dissipation material.

公开(公告)号：US20240071973A1

公开(公告)日：2024-02-29

申请号：US18502389

申请日：2023-11-06

Applicant: Micron Technology, Inc.

Inventor： Wei Zhou

IPC: H01L23/00

CPC classification number: H01L24/16 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/81 ,  H01L24/83 ,  H01L24/91 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05169 ,  H01L2224/05173 ,  H01L2224/05176 ,  H01L2224/05178 ,  H01L2224/0518 ,  H01L2224/05181 ,  H01L2224/05183 ,  H01L2224/05184 ,  H01L2224/05541 ,  H01L2224/11826 ,  H01L2224/11827 ,  H01L2224/11845 ,  H01L2224/11849 ,  H01L2224/13009 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13166 ,  H01L2224/13169 ,  H01L2224/13173 ,  H01L2224/13176 ,  H01L2224/13178 ,  H01L2224/1318 ,  H01L2224/13181 ,  H01L2224/13183 ,  H01L2224/13184 ,  H01L2224/13565 ,  H01L2224/14181 ,  H01L2224/16146 ,  H01L2224/2919 ,  H01L2224/29191 ,  H01L2224/32145 ,  H01L2224/73103 ,  H01L2224/81815 ,  H01L2224/8185 ,  H01L2924/0635 ,  H01L2924/0665 ,  H01L2924/07025

Abstract: A semiconductor device assembly, comprising a first semiconductor device including a first substrate with a frontside surface, a plurality of solder bumps located on the frontside surface of the first substrate, and a first polymer layer on the frontside surface. The semiconductor device assembly also comprises a second semiconductor device including a second substrate with a backside surface, a plurality of TSVs protruding from the backside surface of the second substrate, and a second polymer layer on the backside surface of the first substrate, the second polymer layer having a plurality of openings corresponding to the plurality of TSVs. The first and second semiconductor devices are bonded such that the first polymer layer contacts the second polymer layer and each of the plurality of solder bumps extends into a corresponding one of the plurality of openings and contacts a corresponding one of the plurality of TSVs.

公开(公告)号：US20240047446A1

公开(公告)日：2024-02-08

申请号：US17882626

申请日：2022-08-08

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Mao-Yen Chang ,  Chun-Cheng Lin ,  Chih-Wei Lin ,  Yi-Da Tsai ,  Hsaing-Pin Kuan ,  Chih-Chiang Tsao ,  Hsuan-Ting Kuo ,  Hsiu-Jen Lin ,  Yu-Chia Lai ,  Kuo-Lung Pan ,  Hao-Yi Tsai ,  Ching-Hua Hsieh

IPC: H01L25/18 ,  H01L23/00 ,  H01R12/57 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L25/18 ,  H01L24/19 ,  H01L24/95 ,  H01R12/57 ,  H01L24/13 ,  H01L25/0652 ,  H01L24/20 ,  H01L24/14 ,  H01L24/16 ,  H01L24/81 ,  H01L25/50 ,  H01L24/11 ,  H01L2224/19 ,  H01L2224/95001 ,  H01L2224/214 ,  H01L2224/2101 ,  H01L2224/81815 ,  H01L2224/81201 ,  H01L2224/81862 ,  H01L2224/81193 ,  H01L2224/81906 ,  H01L2224/1403 ,  H01L2224/14517 ,  H01L2224/14505 ,  H01L2224/1319 ,  H01L2924/0665 ,  H01L2924/0635 ,  H01L2924/07025 ,  H01L2224/1329 ,  H01L2224/13386 ,  H01L2924/05442 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13144 ,  H01L2224/16108 ,  H01L2224/16238 ,  H01L2224/16059 ,  H01L2224/13016 ,  H01L2224/1607 ,  H01L2224/8192 ,  H01L2224/1131 ,  H01L2924/1427 ,  H01L2924/14361 ,  H01L2924/1432 ,  H01L2924/1433 ,  H01L2924/1431

Abstract: A semiconductor package and a manufacturing method thereof are described. The semiconductor package includes a package having dies encapsulated by an encapsulant, a redistribution circuit structure, first and second modules and affixing blocks. The redistribution circuit structure is disposed on the package. The first and second modules are disposed on and respectively electrically connected to the redistribution circuit structure by first and second connectors disposed there-between. The first and second modules are adjacent to each other and disposed side by side on the redistribution circuit structure. The affixing blocks are disposed on the redistribution circuit structure and between the first and second modules and the redistribution circuit structure. The affixing blocks include first footing portions located below the first module, second footing portions located below the second module, and exposed portions exposed from the first and second modules. The affixing blocks join the first and second modules to the redistribution circuit structure.

公开(公告)号：US20230282605A1

公开(公告)日：2023-09-07

申请号：US17684292

申请日：2022-03-01

Applicant: Micron Technology, Inc.

Inventor： Wei Zhou

IPC: H01L23/00

CPC classification number: H01L24/16 ,  H01L24/05 ,  H01L24/13 ,  H01L24/14 ,  H01L24/11 ,  H01L24/81 ,  H01L24/83 ,  H01L24/91 ,  H01L2224/05541 ,  H01L2224/13009 ,  H01L2224/14181 ,  H01L2224/13565 ,  H01L2224/11826 ,  H01L2224/11827 ,  H01L2224/11845 ,  H01L2224/11849 ,  H01L2224/16146 ,  H01L24/32 ,  H01L2224/32145 ,  H01L24/73 ,  H01L2224/73103 ,  H01L24/29 ,  H01L2224/2919 ,  H01L2224/29191 ,  H01L2224/13147 ,  H01L2224/13184 ,  H01L2224/1318 ,  H01L2224/13155 ,  H01L2224/13166 ,  H01L2224/13181 ,  H01L2224/13169 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13176 ,  H01L2224/13178 ,  H01L2224/13183 ,  H01L2224/13173 ,  H01L2224/05147 ,  H01L2224/05184 ,  H01L2224/0518 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05169 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05176 ,  H01L2224/05178 ,  H01L2224/05183 ,  H01L2224/05173 ,  H01L2224/81815 ,  H01L2224/8185 ,  H01L2924/0665 ,  H01L2924/0635 ,  H01L2924/07025

Abstract: A semiconductor device assembly, comprising a first semiconductor device including a first substrate with a frontside surface, a plurality of solder bumps located on the frontside surface of the first substrate, and a first polymer layer on the frontside surface. The semiconductor device assembly also comprises a second semiconductor device including a second substrate with a backside surface, a plurality of TSVs protruding from the backside surface of the second substrate, and a second polymer layer on the backside surface of the first substrate, the second polymer layer having a plurality of openings corresponding to the plurality of TSVs. The first and second semiconductor devices are bonded such that the first polymer layer contacts the second polymer layer and each of the plurality of solder bumps extends into a corresponding one of the plurality of openings and contacts a corresponding one of the plurality of TSVs.

公开(公告)号：US20230215854A1

公开(公告)日：2023-07-06

申请号：US18182852

申请日：2023-03-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Jiun Yi Wu ,  Hsing-Kuo Hsia

IPC: H01L23/538 ,  G02B6/122 ,  H01L23/498 ,  H10B80/00 ,  H01L21/48 ,  H01L23/00

CPC classification number: H01L23/5385 ,  G02B6/122 ,  H01L23/49833 ,  H10B80/00 ,  H01L21/4857 ,  H01L24/29 ,  H01L24/32 ,  H01L24/13 ,  H01L24/16 ,  H01L24/73 ,  H01L23/49816 ,  H01L21/4853 ,  H01L2224/16237 ,  H01L2224/13021 ,  H01L2224/81192 ,  H01L2224/81815 ,  H01L2224/32225 ,  H01L2224/83102 ,  H01L2224/2919 ,  H01L2924/0635 ,  H01L2224/73204 ,  H01L24/81 ,  H01L24/83

Abstract: An embodiment device includes: a first dielectric layer; a first photonic die and a second photonic die disposed adjacent a first side of the first dielectric layer; a waveguide optically coupling the first photonic die to the second photonic die, the waveguide being disposed between the first dielectric layer and the first photonic die, and between the first dielectric layer and the second photonic die; a first integrated circuit die and a second integrated circuit die disposed adjacent the first side of the first dielectric layer; conductive features extending through the first dielectric layer and along a second side of the first dielectric layer, the conductive features electrically coupling the first photonic die to the first integrated circuit die, the conductive features electrically coupling the second photonic die to the second integrated circuit die; and a second dielectric layer disposed adjacent the second side of the first dielectric layer.

公开(公告)号：US20180331170A1

公开(公告)日：2018-11-15

申请号：US15553266

申请日：2017-05-25

Applicant: Wuhan China Star Optoelectronics Technology Co., Ltd.

Inventor： Kui XU

IPC: H01L27/32 ,  H01L23/00 ,  H01L23/498 ,  H01L25/18 ,  H05K1/18 ,  H05K1/14 ,  H05K1/11

CPC classification number: H01L27/3276 ,  H01L23/4985 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L25/18 ,  H01L2224/1145 ,  H01L2224/11614 ,  H01L2224/11622 ,  H01L2224/13019 ,  H01L2224/13124 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13166 ,  H01L2224/1318 ,  H01L2224/16148 ,  H01L2224/16238 ,  H01L2224/29028 ,  H01L2224/2929 ,  H01L2224/29298 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2227/323 ,  H01L2924/0635 ,  H01L2924/07025 ,  H01L2924/2064 ,  H05K1/111 ,  H05K1/147 ,  H05K1/189 ,  H05K3/027 ,  H05K3/4007 ,  H05K2201/10128 ,  H05K2201/1078 ,  H05K2201/10787 ,  H05K2201/10977

Abstract: The present invention discloses a connection component, connector, manufacturing method for the same and panel component. The connection component includes a first connector and a second connector electrically connected to the first connector, wherein, between the first connector and the second connector, a connection adhesive is provided, the first connector and/or the second connector both include a base body and multiple connection terminals, wherein the multiple connection terminals are disposed on the base body, a terminal portion of each connection terminal has a protrusion, the protrusion has a saw-tooth shape, and the saw-tooth shape has a regular pattern or a non-regular pattern, Accordingly, the present invention can enhance the reliability of the connection and increase the production yield.

公开(公告)号：US20180277510A1

公开(公告)日：2018-09-27

申请号：US15813676

申请日：2017-11-15

Applicant: International Business Machines Corporation

Inventor： ERIC J. CAMPBELL ,  SARAH K. CZAPLEWSKI ,  ELIN LABRECK ,  JENNIFER I. PORTO

IPC: H01L23/00 ,  C09K5/10 ,  H01L23/373 ,  H01L23/367

CPC classification number: H01L24/83 ,  C09K5/10 ,  H01L23/367 ,  H01L23/3675 ,  H01L23/3737 ,  H01L23/42 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L2224/271 ,  H01L2224/2731 ,  H01L2224/2755 ,  H01L2224/2783 ,  H01L2224/2919 ,  H01L2224/29191 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/83101 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83193 ,  H01L2224/83201 ,  H01L2224/83874 ,  H01L2224/83986 ,  H01L2924/0635 ,  H01L2924/0665 ,  H01L2924/0715 ,  H01L2924/1434 ,  H01L2924/20211 ,  H01L2924/20212 ,  H01L2924/20213 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/0625

Abstract: A process of forming a thermal interface material structure includes selectively masking a putty pad that includes ultraviolet (UV) curable cross-linkers to form a masked putty pad. The masked putty pad has a first area that is exposed and a second area that is masked. The process also includes exposing the masked putty pad to UV light to form a selectively cross-linked putty pad. The process includes disposing the selectively cross-linked putty pad between an electrical component and a heat spreader to form an assembly. The process further includes compressing the assembly to form a thermal interface material structure that includes a selectively cross-linked thermal interface material.

公开(公告)号：US20180079939A1

公开(公告)日：2018-03-22

申请号：US15532931

申请日：2016-02-05

Applicant: DEXERIALS CORPORATION

Inventor： Kenji KUBOTA ,  Takayuki SAITO

IPC: C09J163/08 ,  C09J7/00 ,  C09J133/16 ,  H01L23/00 ,  H01L21/56 ,  H01L23/29 ,  H01L23/31

CPC classification number: C09J163/08 ,  C08G59/42 ,  C09J7/00 ,  C09J133/04 ,  C09J133/16 ,  C09J163/00 ,  C09J2203/326 ,  C09J2433/00 ,  C09J2463/00 ,  H01L21/563 ,  H01L23/293 ,  H01L23/3157 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/75 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16148 ,  H01L2224/16238 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/75252 ,  H01L2224/7598 ,  H01L2224/75981 ,  H01L2224/81005 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/81907 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83203 ,  H01L2224/83862 ,  H01L2224/83907 ,  H01L2224/92 ,  H01L2224/9211 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06568 ,  H01L2924/0665 ,  H01L2924/18161 ,  H01L2924/364 ,  H01L2924/384 ,  C08K5/18 ,  C08L33/08 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/095 ,  H01L2924/0635 ,  H01L2924/01083 ,  H01L2924/01082 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/01051 ,  H01L2224/27 ,  H01L2224/11 ,  H01L21/78 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: A method for manufacturing a semiconductor device and an underfill film which can achieve voidless mounting and excellent solder bonding properties even in the case of collectively bonding a plurality of semiconductor chips are provided. The method includes a mounting step of mounting a plurality of semiconductor chips having a solder-tipped electrode onto an electronic component having a counter electrode opposing the solder-tipped electrode via an underfill film; and a compression bonding step of collectively bonding the plurality of semiconductor chips to the electronic component via the underfill film. The underfill film contains an epoxy resin, an acid anhydride, an acrylic resin, and an organic peroxide and has a minimum melt viscosity of 1,000 to 2,000 Pa*s and a melt viscosity gradient of 900 to 3,100 Pa*s/° C. from a temperature 10° C. higher than a minimum melt viscosity attainment temperature to a temperature 10° C. higher than the temperature.

公开(公告)号：US20180012859A1

公开(公告)日：2018-01-11

申请号：US15713008

申请日：2017-09-22

Applicant: Infineon Technologies Americas Corp.

Inventor： Martin Standing

IPC: H01L23/00 ,  H01L23/04 ,  H01L23/06 ,  H01L23/498 ,  H01L23/14 ,  H01L23/492 ,  H01L23/495 ,  H01L25/16 ,  H01L23/13

CPC classification number: H01L24/40 ,  H01L23/04 ,  H01L23/06 ,  H01L23/13 ,  H01L23/14 ,  H01L23/492 ,  H01L23/4924 ,  H01L23/49548 ,  H01L23/49558 ,  H01L23/49582 ,  H01L23/4985 ,  H01L24/24 ,  H01L24/34 ,  H01L24/36 ,  H01L24/37 ,  H01L24/82 ,  H01L24/83 ,  H01L24/84 ,  H01L25/165 ,  H01L2224/24227 ,  H01L2224/32245 ,  H01L2224/37012 ,  H01L2224/37147 ,  H01L2224/37639 ,  H01L2224/37644 ,  H01L2224/40225 ,  H01L2224/73153 ,  H01L2224/73253 ,  H01L2224/76155 ,  H01L2224/82102 ,  H01L2224/8385 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01045 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01084 ,  H01L2924/014 ,  H01L2924/05432 ,  H01L2924/0635 ,  H01L2924/0665 ,  H01L2924/07025 ,  H01L2924/0715 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/14 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49147 ,  Y10T29/49155 ,  Y10T29/49174 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A semiconductor package that includes a conductive can, a power semiconductor device electrically and mechanically attached to the inside surface of the can, and an IC semiconductor device copackaged with the power semiconductor device inside the can.

公开(公告)号：US20170358549A1

公开(公告)日：2017-12-14

申请号：US15543113

申请日：2016-01-13

Applicant: DEXERIALS CORPORATION

Inventor： Seiichiro SHINOHARA ,  Yasushi AKUTSU ,  Tomoyuki ISHIMATSU

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L24/27 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/11003 ,  H01L2224/111 ,  H01L2224/13078 ,  H01L2224/1308 ,  H01L2224/131 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13157 ,  H01L2224/13164 ,  H01L2224/1319 ,  H01L2224/133 ,  H01L2224/13686 ,  H01L2224/1369 ,  H01L2224/1403 ,  H01L2224/16058 ,  H01L2224/16059 ,  H01L2224/16146 ,  H01L2224/16147 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/17107 ,  H01L2224/27003 ,  H01L2224/271 ,  H01L2224/27515 ,  H01L2224/29082 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29387 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73104 ,  H01L2224/81101 ,  H01L2224/81122 ,  H01L2224/81903 ,  H01L2224/83101 ,  H01L2224/83122 ,  H01L2224/83203 ,  H01L2224/83856 ,  H01L2224/9211 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/06589 ,  H01L2924/00015 ,  H01L2924/3841 ,  H01L2224/83851 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/0635 ,  H01L2924/0665 ,  H01L2924/05442 ,  H01L2924/05432

Abstract: Provided is a multilayer substrate including laminated semiconductor substrates each having a penetrating hole (hereinafter referred to as through hole) having a plated film formed in the inner surface. The multilayer substrate has excellent conduction characteristics and can be manufactured at low cost. Conductive particles are selectively present at a position where the through holes face each other as viewed in a plan view of the multilayer substrate. The multilayer substrate has a connection structure in which the facing through holes are connected by the conductive particles, and the semiconductor substrates each having the through hole are bonded by an insulating adhesive.