公开(公告)号：US20240332227A1

公开(公告)日：2024-10-03

申请号：US18194544

申请日：2023-03-31

Applicant: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC

Inventor： Cyprian Emeka Uzoh ,  Oliver Zhao

IPC: H01L23/00

CPC classification number: H01L24/05 ,  H01L24/03 ,  H01L24/08 ,  H01L2224/03614 ,  H01L2224/0382 ,  H01L2224/03826 ,  H01L2224/03827 ,  H01L2224/03845 ,  H01L2224/05026 ,  H01L2224/05073 ,  H01L2224/05157 ,  H01L2224/05166 ,  H01L2224/0517 ,  H01L2224/05176 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05186 ,  H01L2224/05562 ,  H01L2224/05567 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/05638 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05684 ,  H01L2224/08145 ,  H01L2924/01014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/0496 ,  H01L2924/0543

Abstract: A semiconductor element having an interconnect bonding layer with a contact pad and a plasma damage-free low-k dielectric material is disclosed. The contact pad connects an underlying conductive feature through an intervening via. A thin dielectric layer is disposed on and covering the entire sidewalls of the contact pad, the intervening via and the underlying conductive feature, and making an approximately right angle turn to extend along an interface between the low-k dielectric material and a first dielectric layer that at least partially bury the underlying contact feature.

公开(公告)号：US20230411294A1

公开(公告)日：2023-12-21

申请号：US18457000

申请日：2023-08-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Saehan PARK ,  Hoonseok Seo ,  Jeonghyuk Yim ,  Ki-il Kim ,  Gil Hwan Son

IPC: H01L23/528 ,  H01L21/768 ,  H01L21/822 ,  H01L23/48 ,  H01L23/00 ,  H01L27/06

CPC classification number: H01L23/5286 ,  H01L21/76898 ,  H01L21/8221 ,  H01L23/481 ,  H01L24/05 ,  H01L27/0694 ,  H01L2224/05025 ,  H01L2224/05147 ,  H01L2224/05157 ,  H01L2224/05176

Abstract: Provided is a semiconductor architecture including a carrier substrate, a landing pad included in the carrier substrate, a first semiconductor device provided on a first surface of the carrier substrate, the first semiconductor device including a first component provided on the landing pad, and a second semiconductor device provided on a second surface of the carrier substrate, a second component protruding from the second semiconductor device being provided on the landing pad.

公开(公告)号：US10083924B2

公开(公告)日：2018-09-25

申请号：US14891319

申请日：2014-11-13

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kazuyoshi Maekawa ,  Yuichi Kawano

IPC: H01L23/12 ,  H01L23/00 ,  H01L21/3205 ,  H01L23/522 ,  H01L21/768

CPC classification number: H01L24/02 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/522 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/02166 ,  H01L2224/02181 ,  H01L2224/02185 ,  H01L2224/0219 ,  H01L2224/02331 ,  H01L2224/0235 ,  H01L2224/02373 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/03462 ,  H01L2224/03466 ,  H01L2224/0347 ,  H01L2224/035 ,  H01L2224/03614 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05007 ,  H01L2224/05008 ,  H01L2224/05025 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05157 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05176 ,  H01L2224/0518 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05548 ,  H01L2224/05566 ,  H01L2224/05567 ,  H01L2224/05664 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/4502 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45565 ,  H01L2224/45664 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48664 ,  H01L2224/48864 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/04941 ,  H01L2924/07025 ,  H01L2924/10253 ,  H01L2924/1306 ,  H01L2924/15183 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/01008

Abstract: A semiconductor device includes: a pad electrode 9a formed in an uppermost layer of a plurality of wiring layers; a base insulating film 11 having an opening 11a on the pad electrode 9a; a base metal film UM formed on the base insulating film 11; a redistribution line RM formed on the base metal film UM; and a cap metal film CM formed so as to cover an upper surface and a side surface of the redistribution line RM. In addition, in a region outside the redistribution line RM, the base metal film UM made of a material different from that of the redistribution line RM and the cap metal film CM made of a material different from the redistribution line RM are formed between the cap metal film CM formed on the side surface of the redistribution line RM and the base insulating film 11, and the base metal film UM and the cap metal film CM are in direct contact with each other in the region outside the redistribution line RM.

公开(公告)号：US09978710B2

公开(公告)日：2018-05-22

申请号：US15385653

申请日：2016-12-20

Applicant: IMEC VZW ,  Katholieke Universiteit Leuven

Inventor： Vikas Dubey ,  Eric Beyne ,  Jaber Derakhshandeh

IPC: H01L23/00 ,  H01L23/498 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L24/81 ,  H01L23/291 ,  H01L23/293 ,  H01L23/3192 ,  H01L23/49827 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/03424 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/03616 ,  H01L2224/0401 ,  H01L2224/05018 ,  H01L2224/05026 ,  H01L2224/05082 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05157 ,  H01L2224/05166 ,  H01L2224/05176 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05186 ,  H01L2224/05541 ,  H01L2224/05558 ,  H01L2224/05559 ,  H01L2224/05571 ,  H01L2224/05611 ,  H01L2224/0601 ,  H01L2224/1191 ,  H01L2224/13005 ,  H01L2224/13009 ,  H01L2224/13014 ,  H01L2224/13022 ,  H01L2224/13124 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13184 ,  H01L2224/13541 ,  H01L2224/13562 ,  H01L2224/1357 ,  H01L2224/13644 ,  H01L2224/13655 ,  H01L2224/13657 ,  H01L2224/16058 ,  H01L2224/16112 ,  H01L2224/16146 ,  H01L2224/16147 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/75251 ,  H01L2224/8114 ,  H01L2224/81143 ,  H01L2224/81191 ,  H01L2224/8181 ,  H01L2224/81815 ,  H01L2224/81907 ,  H01L2224/83191 ,  H01L2224/8385 ,  H01L2224/92225 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/049 ,  H01L2924/053 ,  H01L2924/01049 ,  H01L2924/014 ,  H01L2924/01047 ,  H01L2924/01083 ,  H01L2924/01005 ,  H01L2924/206 ,  H01L2924/20106 ,  H01L2924/207

Abstract: A method for producing a stack of semiconductor devices and the stacked device obtained thereof are disclosed. In one aspect, the method includes providing a first semiconductor device comprising a dielectric layer with a hole, the hole lined with a metal layer and partially filled with solder material. The method also includes providing a second semiconductor device with a compliant layer having a metal protrusion through the compliant layer, the protrusion capped with a capping layer. The method further includes mounting the devices by landing the metal protrusion in the hole, where the compliant layer is spaced from the dielectric layer. The method includes thereafter reflowing the solder material, thereby bonding the devices such that the compliant layer is contacting the dielectric layer.

公开(公告)号：US20180005967A1

公开(公告)日：2018-01-04

申请号：US15704024

申请日：2017-09-14

Applicant: Renesas Electronics Corporation

Inventor： Akira YAJIMA

IPC: H01L23/00

CPC classification number: H01L24/02 ,  H01L23/293 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/43 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/02166 ,  H01L2224/02315 ,  H01L2224/02331 ,  H01L2224/0236 ,  H01L2224/02373 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/04042 ,  H01L2224/05008 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05169 ,  H01L2224/05171 ,  H01L2224/05176 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05644 ,  H01L2224/4502 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48463 ,  H01L2924/01029 ,  H01L2924/07025 ,  H01L2924/364 ,  H01L2924/365 ,  H01L2924/00014 ,  H01L2924/00015 ,  H01L2924/01007 ,  H01L2924/01074 ,  H01L2924/01014 ,  H01L2924/013 ,  H01L2924/00013

Abstract: Reliability of a semiconductor device is improved. A slope is provided on a side face of an interconnection trench in sectional view in an interconnection width direction of a redistribution layer. The maximum opening width of the interconnection trench in the interconnection width direction is larger than the maximum interconnection width of the redistribution layer in the interconnection width direction, and the interconnection trench is provided so as to encapsulate the redistribution layer in plan view.

公开(公告)号：US20160276558A1

公开(公告)日：2016-09-22

申请号：US14412794

申请日：2014-12-16

Applicant: ILJIN LED CO., LTD.

Inventor： Pil Geun KANG ,  Ho Sub LEE ,  Seong Joo HWANG

IPC: H01L33/62 ,  H01L33/06 ,  H01L33/46

CPC classification number: H01L33/62 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L33/06 ,  H01L33/46 ,  H01L2224/0401 ,  H01L2224/05018 ,  H01L2224/05019 ,  H01L2224/0508 ,  H01L2224/05109 ,  H01L2224/05111 ,  H01L2224/05118 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05157 ,  H01L2224/0516 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05169 ,  H01L2224/0517 ,  H01L2224/05171 ,  H01L2224/05172 ,  H01L2224/05173 ,  H01L2224/05176 ,  H01L2224/0518 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05193 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05664 ,  H01L2224/05669 ,  H01L2224/05676 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16225 ,  H01L2224/16245 ,  H01L2224/81801 ,  H01L2224/81805 ,  H01L2933/0066 ,  H01L2924/0105

Abstract: A light-emitting diode having a multilayer bonding pad includes: a P1 layer disposed under a light-emitting structure and configured to improve ohmic contact and adhesion; a P3 layer disposed under the P1 layer and configured to prevent diffusion; a Sn-based metal layer disposed under the P1 layer and configured to enhance soldering weldability and prevent oxidation; a Cu-based P5 layer disposed on the Sn-based metal layer and configured to prevent the diffusion of Sn; and a P4 layer disposed between the P3 layer and the P5 layer and configured to suppress the reaction between the P5 layer and other layers.

Abstract translation: 具有多层接合焊盘的发光二极管包括：设置在发光结构下并被配置为改善欧姆接触和粘附的P1层; P3层，其设置在所述P1层下方并且被配置为防止扩散; 设置在P1层下方的Sn系金属层，其构造为提高焊接性，防止氧化; 设置在所述Sn基金属层上并且被配置为防止Sn的扩散的Cu基P5层; 以及设置在P3层和P5层之间的P4层，并且被配置为抑制P5层与其它层之间的反应。

公开(公告)号：US20090057895A1

公开(公告)日：2009-03-05

申请号：US12264271

申请日：2008-11-04

Applicant: Mou-Shiung Lin ,  Chien-Kang Chou ,  Ke-Hung Chen

Inventor： Mou-Shiung Lin ,  Chien-Kang Chou ,  Ke-Hung Chen

IPC: H01L23/488

CPC classification number: H01L23/5227 ,  H01L21/2885 ,  H01L21/563 ,  H01L21/76801 ,  H01L21/76885 ,  H01L23/3114 ,  H01L23/5223 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L24/83 ,  H01L2224/0347 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05173 ,  H01L2224/05176 ,  H01L2224/05183 ,  H01L2224/05548 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05664 ,  H01L2224/05669 ,  H01L2224/1147 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/16 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45155 ,  H01L2224/45164 ,  H01L2224/45169 ,  H01L2224/45173 ,  H01L2224/45176 ,  H01L2224/45183 ,  H01L2224/48091 ,  H01L2224/48463 ,  H01L2224/48639 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/48664 ,  H01L2224/48669 ,  H01L2224/48839 ,  H01L2224/48844 ,  H01L2224/48847 ,  H01L2224/48864 ,  H01L2224/83101 ,  H01L2224/83192 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/09701 ,  H01L2924/10329 ,  H01L2924/12044 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2224/48869 ,  H01L2224/83851 ,  H01L2224/05552 ,  H01L2224/05599

Abstract: A post passivation rerouting support structure comprises a relatively thin support layer above the passivation layer to support the RDL, and a relatively thick support layer for fine pitch interconnects extending from the RDL and terminating as contact structures at the surface of the thick support layer, for a next level packaging structure. The thick support layer is planarized before defining the contact structures. The thick support layer may be formed after the conducting posts have been formed, or the thick support layer is formed before forming the conducting posts in vias formed in the thick support layer. An encapsulating layer may be provided above the thick support layer, which top surface is planarized before defining the contact structures. The encapsulating layer and the further support layer may be the same layer.

Abstract translation: 后钝化重路由支持结构包括钝化层上方相对薄的支撑层以支撑RDL，以及用于从RDL延伸并作为接触结构终止于厚支撑层表面的细间距互连的相对较厚的支撑层，用于 下一级包装结构。 在限定接触结构之前，将厚支撑层平坦化。 可以在形成导电柱之后形成厚的支撑层，或者在形成在厚支撑层中的通孔中形成导电柱之前形成厚的支撑层。 可以在厚支撑层之上设置封装层，在限定接触结构之前该顶表面被平坦化。 封装层和另外的支撑层可以是相同的层。

公开(公告)号：US07468545B2

公开(公告)日：2008-12-23

申请号：US11430513

申请日：2006-05-08

Applicant: Mou-Shiung Lin ,  Chien-Kang Chou ,  Ke-Hung Chen

Inventor： Mou-Shiung Lin ,  Chien-Kang Chou ,  Ke-Hung Chen

IPC: H01L29/06

CPC classification number: H01L23/5227 ,  H01L21/2885 ,  H01L21/563 ,  H01L21/76801 ,  H01L21/76885 ,  H01L23/3114 ,  H01L23/5223 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L24/83 ,  H01L2224/0347 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05173 ,  H01L2224/05176 ,  H01L2224/05183 ,  H01L2224/05548 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05664 ,  H01L2224/05669 ,  H01L2224/1147 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/16 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45155 ,  H01L2224/45164 ,  H01L2224/45169 ,  H01L2224/45173 ,  H01L2224/45176 ,  H01L2224/45183 ,  H01L2224/48091 ,  H01L2224/48463 ,  H01L2224/48639 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/48664 ,  H01L2224/48669 ,  H01L2224/48839 ,  H01L2224/48844 ,  H01L2224/48847 ,  H01L2224/48864 ,  H01L2224/83101 ,  H01L2224/83192 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/09701 ,  H01L2924/10329 ,  H01L2924/12044 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2224/48869 ,  H01L2224/83851 ,  H01L2224/05552 ,  H01L2224/05599

Abstract: A post passivation rerouting support structure comprises a relatively thin support layer above the passivation layer to support the RDL, and a relatively thick support layer for fine pitch interconnects extending from the RDL and terminating as contact structures at the surface of the thick support layer, for a next level packaging structure. The thick support layer is planarized before defining the contact structures. The thick support layer may be formed after the conducting posts have been formed, or the thick support layer is formed before forming the conducting posts in vias formed in the thick support layer. An encapsulating layer may be provided above the thick support layer, which top surface is planarized before defining the contact structures. The encapsulating layer and the further support layer may be the same layer.

Abstract translation: 后钝化重路由支持结构包括钝化层上方相对薄的支撑层以支撑RDL，以及用于从RDL延伸并作为接触结构终止于厚支撑层表面的细间距互连的相对较厚的支撑层，用于 下一级包装结构。 在限定接触结构之前，将厚支撑层平坦化。 可以在形成导电柱之后形成厚的支撑层，或者在形成在厚支撑层中的通孔中形成导电柱之前形成厚的支撑层。 可以在厚支撑层之上设置封装层，在限定接触结构之前该顶表面被平坦化。 封装层和另外的支撑层可以是相同的层。

公开(公告)号：US11923326B2

公开(公告)日：2024-03-05

申请号：US17875291

申请日：2022-07-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Ching-Yu Chang ,  Ming-Da Cheng ,  Ming-Hui Weng

IPC: H01L23/00 ,  C08G73/10

CPC classification number: H01L24/05 ,  C08G73/1078 ,  C08G73/1085 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02251 ,  H01L2224/0226 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03616 ,  H01L2224/0401 ,  H01L2224/05111 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05176 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/11462 ,  H01L2224/11849 ,  H01L2224/13026 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13118 ,  H01L2224/1312 ,  H01L2224/13123 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13149 ,  H01L2224/13155 ,  H01L2224/1316 ,  H01L2224/13166 ,  H01L2224/13171 ,  H01L2224/13179 ,  H01L2224/1318 ,  H01L2224/13181 ,  H01L2224/13184 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/07025

Abstract: A method of manufacturing a bump structure includes forming a passivation layer over a substrate. A metal pad structure is formed over the substrate, wherein the passivation layer surrounds the metal pad structure. A polyimide layer including a polyimide is formed over the passivation layer and the metal pad structure. A metal bump is formed over the metal pad structure and the polyimide layer. The polyimide is a reaction product of a dianhydride and a diamine, wherein at least one of the dianhydride and the diamine comprises one selected from the group consisting of a cycloalkane, a fused ring, a bicycloalkane, a tricycloalkane, a bicycloalkene, a tricycloalkene, a spiroalkane, and a heterocyclic ring.

公开(公告)号：US20240071973A1

公开(公告)日：2024-02-29

申请号：US18502389

申请日：2023-11-06

Applicant: Micron Technology, Inc.

Inventor： Wei Zhou

IPC: H01L23/00

CPC classification number: H01L24/16 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/81 ,  H01L24/83 ,  H01L24/91 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05169 ,  H01L2224/05173 ,  H01L2224/05176 ,  H01L2224/05178 ,  H01L2224/0518 ,  H01L2224/05181 ,  H01L2224/05183 ,  H01L2224/05184 ,  H01L2224/05541 ,  H01L2224/11826 ,  H01L2224/11827 ,  H01L2224/11845 ,  H01L2224/11849 ,  H01L2224/13009 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13166 ,  H01L2224/13169 ,  H01L2224/13173 ,  H01L2224/13176 ,  H01L2224/13178 ,  H01L2224/1318 ,  H01L2224/13181 ,  H01L2224/13183 ,  H01L2224/13184 ,  H01L2224/13565 ,  H01L2224/14181 ,  H01L2224/16146 ,  H01L2224/2919 ,  H01L2224/29191 ,  H01L2224/32145 ,  H01L2224/73103 ,  H01L2224/81815 ,  H01L2224/8185 ,  H01L2924/0635 ,  H01L2924/0665 ,  H01L2924/07025

Abstract: A semiconductor device assembly, comprising a first semiconductor device including a first substrate with a frontside surface, a plurality of solder bumps located on the frontside surface of the first substrate, and a first polymer layer on the frontside surface. The semiconductor device assembly also comprises a second semiconductor device including a second substrate with a backside surface, a plurality of TSVs protruding from the backside surface of the second substrate, and a second polymer layer on the backside surface of the first substrate, the second polymer layer having a plurality of openings corresponding to the plurality of TSVs. The first and second semiconductor devices are bonded such that the first polymer layer contacts the second polymer layer and each of the plurality of solder bumps extends into a corresponding one of the plurality of openings and contacts a corresponding one of the plurality of TSVs.