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1.发明公开公开(公告)号：US20230411294A1
公开(公告)日：2023-12-21
申请号：US18457000
申请日：2023-08-28
发明人： Saehan PARK , Hoonseok Seo , Jeonghyuk Yim , Ki-il Kim , Gil Hwan Son
IPC分类号： H01L23/528 , H01L21/768 , H01L21/822 , H01L23/48 , H01L23/00 , H01L27/06
CPC分类号： H01L23/5286 , H01L21/76898 , H01L21/8221 , H01L23/481 , H01L24/05 , H01L27/0694 , H01L2224/05025 , H01L2224/05147 , H01L2224/05157 , H01L2224/05176
摘要： Provided is a semiconductor architecture including a carrier substrate, a landing pad included in the carrier substrate, a first semiconductor device provided on a first surface of the carrier substrate, the first semiconductor device including a first component provided on the landing pad, and a second semiconductor device provided on a second surface of the carrier substrate, a second component protruding from the second semiconductor device being provided on the landing pad.
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公开(公告)号：US20230086084A1
公开(公告)日：2023-03-23
申请号：US17554483
申请日：2021-12-17
发明人： Seungchan Yun , Inchan Hwang , Gunho Jo , Jeonghyuk Yim , Byounghak Hong , Kang-ill Seo , Ming He , JaeHyun Park , Mehdi Saremi , Rebecca Park , Harsono Simka , Daewon Ha
IPC分类号： H01L29/423 , H01L29/06 , H01L29/786 , H01L27/088 , H01L29/417 , H01L21/8234
摘要： Transistor devices are provided. A transistor device includes a substrate. The transistor device includes a lower transistor having a lower gate and a lower channel region on the substrate. The transistor device includes an upper transistor having an upper gate and an upper channel region. The lower transistor is between the upper transistor and the substrate. The transistor device includes an isolation region that separates the lower channel region of the lower transistor from the upper channel region of the upper transistor. Moreover, the lower gate of the lower transistor contacts the upper gate of the upper transistor. Related methods of forming a transistor device are also provided.
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公开(公告)号：US20220230924A1
公开(公告)日：2022-07-21
申请号：US17223803
申请日：2021-04-06
发明人： Jeonghyuk Yim , Kang III Seo
IPC分类号： H01L21/8234 , H01L27/088 , H01L29/78 , H01L21/3065 , H01L21/308 , H01L29/66
摘要： Provided is a vertical field-effect transistor (VFET) device which includes: a substrate; a plurality of single-fin VFETs including respective 1st fin structures on the substrate; and a plurality of multi-fin VFETs each of which includes a plurality of 2nd fin structures on the substrate, wherein a fin pitch of the 2nd fin structures is smaller than a fin pitch of the 1st fin structures.
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公开(公告)号：US20240222451A1
公开(公告)日：2024-07-04
申请号：US18243818
申请日：2023-09-08
发明人： Wandon Kim , Jaeseoung Park , Hyunwoo Kim , Hyunbae Lee , Jeonghyuk Yim , Hyoseok Choi
IPC分类号： H01L29/417 , H01L29/06 , H01L29/423 , H01L29/775 , H01L29/786
CPC分类号： H01L29/41733 , H01L29/0673 , H01L29/41775 , H01L29/42392 , H01L29/775 , H01L29/78696
摘要： A semiconductor device includes an active region extending in a first direction, a gate structure extending in a second direction, a source/drain region on the active region, a first contact structure connected to the source/drain region, and a second contact structure connected to the first contact structure. The second contact structure includes a first layer including a first grain and a second layer including second grains on the first layer. Within the first layer, a maximum vertical distance between a lowermost end of the first grain and an uppermost end of the first grain is equal to a vertical distance between a lowermost end of the first layer and an uppermost end of the first layer. A size of the first grain is greater than a size of each of the second grains. A width of the first layer is greater than a width of the first contact structure.
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公开(公告)号：US11901240B2
公开(公告)日：2024-02-13
申请号：US17223803
申请日：2021-04-06
发明人： Jeonghyuk Yim , Kang Ill Seo
IPC分类号： H01L21/8234 , H01L27/088 , H01L29/78 , H01L21/3065 , H01L21/308 , H01L29/66
CPC分类号： H01L21/823487 , H01L21/308 , H01L21/3065 , H01L21/823412 , H01L21/823437 , H01L21/823481 , H01L27/088 , H01L29/66666 , H01L29/7827
摘要： Provided is a vertical field-effect transistor (VFET) device which includes: a substrate; a plurality of single-fin VFETs including respective 1st fin structures on the substrate; and a plurality of multi-fin VFETs each of which includes a plurality of 2nd fin structures on the substrate, wherein a fin pitch of the 2nd fin structures is smaller than a fin pitch of the 1st fin structures.
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公开(公告)号：US11557656B2
公开(公告)日：2023-01-17
申请号：US17024813
申请日：2020-09-18
发明人： Jonghan Lee , Wandon Kim , Jaeyeol Song , Jeonghyuk Yim , HyungSuk Jung
IPC分类号： H01L29/423 , H01L27/088 , H01L29/51 , H01L29/66 , H01L21/28 , H01L21/8234 , H01L21/768
摘要： Disclosed are semiconductor devices and methods of manufacturing the same. The semiconductor device comprises a gate electrode on a substrate, an upper capping pattern on the gate electrode, and a lower capping pattern between the gate electrode and the upper capping pattern. The lower capping pattern comprises a first portion between the gate electrode and the upper capping pattern, and a plurality of second portions extending from the first portion onto corresponding side surfaces of the upper capping pattern. The upper capping pattern covers a topmost surface of each of the second portions.
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7.发明申请公开(公告)号：US20220157723A1
公开(公告)日：2022-05-19
申请号：US17159972
申请日：2021-01-27
发明人： Saehan Park , Hoonseok Seo , Jeonghyuk Yim , Ki-il Kim , Gil Hwan Son
IPC分类号： H01L23/528 , H01L27/06 , H01L23/48 , H01L23/00 , H01L21/768 , H01L21/822
摘要： Provided is a semiconductor architecture including a carrier substrate, a landing pad included in the carrier substrate, a first semiconductor device provided on a first surface of the carrier substrate, the first semiconductor device including a first component provided on the landing pad, and a second semiconductor device provided on a second surface of the carrier substrate, a second component protruding from the second semiconductor device being provided on the landing pad.
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公开(公告)号：US11923365B2
公开(公告)日：2024-03-05
申请号：US17387178
申请日：2021-07-28
发明人： Jeonghyuk Yim , Ki-Il Kim , Gil Hwan Son , Kang Ill Seo
IPC分类号： H01L27/092 , H01L21/8238 , H01L29/06 , H01L29/40 , H01L29/423 , H01L29/66 , H01L29/786
CPC分类号： H01L27/0922 , H01L21/82385 , H01L21/823857 , H01L21/823871 , H01L29/0665 , H01L29/401 , H01L29/42368 , H01L29/42376 , H01L29/42392 , H01L29/66742 , H01L29/78645
摘要： Integrated circuit devices may include two transistor stacks including lower transistors having different threshold voltages and upper transistors having different threshold voltages. Gate insulators of the lower transistors may have different dipole elements or different areal densities of dipole elements, and the upper transistors may have different gate electrode structures.
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公开(公告)号：US11094586B2
公开(公告)日：2021-08-17
申请号：US16539064
申请日：2019-08-13
发明人： Seung Hoon Choi , Jaeung Koo , Kwansung Kim , Bo Yun Kim , Wandon Kim , Boun Yoon , Jeonghyuk Yim , Yeryung Jeon
IPC分类号： H01L21/768 , H01L27/105 , H01L23/528 , H01L23/532 , H01L21/3105
摘要： A semiconductor device and a method of fabricating a semiconductor device, the semiconductor device including a semiconductor substrate including a first region and a second region; an interlayer insulating layer on the semiconductor substrate, the interlayer insulating layer including a first opening on the first region and having a first width; and a second opening on the second region and having a second width, the second width being greater than the first width; at least one first metal pattern filling the first opening; a second metal pattern in the second opening; and a filling pattern on the second metal pattern in the second opening, wherein the at least one first metal pattern and the second metal pattern each include a same first metal material, and the filling pattern is formed of a non-metal material.
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公开(公告)号：US10950709B2
公开(公告)日：2021-03-16
申请号：US16458412
申请日：2019-07-01
发明人： Jeonghyuk Yim , Wandon Kim , Weonhong Kim , Jongho Park , Hyeonjun Baek , Byounghoon Lee , Sangjin Hyun
IPC分类号： H01L29/78 , H01L27/092 , H01L29/06 , H01L29/423 , H01L29/49 , H01L29/786 , H01L29/51 , H01L21/28 , H01L29/66 , H01L21/8238 , H01L29/08
摘要： A semiconductor device includes a substrate including first and second active regions, first and second active patterns disposed on the first and second active regions, respectively, first and second gate electrodes crossing the first and second active patterns, respectively, a first gate insulating pattern interposed between the first active pattern and the first gate electrode, and a second gate insulating pattern interposed between the second active pattern and the second gate electrode. The first gate insulating pattern includes a first dielectric pattern and a first ferroelectric pattern disposed on the first dielectric pattern. The second gate insulating pattern includes a second dielectric pattern. A threshold voltage of a transistor in the first active region is different from a threshold voltage of a transistor in the second active region.
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