公开(公告)号：US11935922B2

公开(公告)日：2024-03-19

申请号：US17970777

申请日：2022-10-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byounghak Hong ,  Seunghyun Song ,  Kang Ill Seo ,  Hwichan Jun ,  Inchan Hwang

IPC: H01L29/06 ,  H01L27/092 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L29/0665 ,  H01L27/092 ,  H01L29/41775 ,  H01L29/42392 ,  H01L29/78696

Abstract: A semiconductor device include: a substrate; a 1st transistor formed above the substrate, the 1st transistor including a 1st channel set of a plurality of 1st nanosheet layers, a 1st gate structure surrounding the 1st nanosheet layers, and 1st and 2nd source/drain regions at both ends of the 1st channel set; and a 2nd transistor formed above the 1st transistor in a vertical direction, the 2nd transistor including a 2nd channel set of a plurality of 2nd nanosheet layers, a 2nd gate structure surrounding the 2nd nanosheet layers, and 3rd and 4th source/drain regions at both ends of the 2nd channel set, wherein the 1st channel set has a greater width than the 2nd channel set, wherein a number of the 1st nanosheet layers is smaller than a number of the 2nd nanosheet layers, and wherein a sum of effective channel widths of the 1st nanosheet layers is substantially equal to a sum of effective channel width of the 2nd nanosheet layers.

公开(公告)号：US11843001B2

公开(公告)日：2023-12-12

申请号：US17380999

申请日：2021-07-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byounghak Hong ,  Seunghyun Song ,  Ki-Il Kim ,  Gunho Jo ,  Kang-Ill Seo

IPC: H04L45/745 ,  H04L12/46 ,  H04L45/52 ,  H01L27/12 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/822 ,  H01L21/84

CPC classification number: H01L27/1203 ,  H01L21/8221 ,  H01L21/823412 ,  H01L21/823456 ,  H01L21/84 ,  H01L27/088

Abstract: Nanosheet transistor devices are provided. A nanosheet transistor device includes a transistor stack that includes a lower nanosheet transistor having a first nanosheet width and a lower gate width. The transistor stack also includes an upper nanosheet transistor that is on the lower nanosheet transistor and that has a second nanosheet width and an upper gate width that are different from the first nanosheet width and the lower gate width, respectively. Related methods of forming a nanosheet transistor device are also provided.

公开(公告)号：US20230326858A1

公开(公告)日：2023-10-12

申请号：US17887203

申请日：2022-08-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Buhyun HAM ,  Byounghak Hong ,  Myunghoon Jung ,  Wonhyuk Hong ,  Seungyoung Lee ,  Kang-ill Seo

IPC: H01L23/535 ,  H01L23/528 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L23/535 ,  H01L23/5286 ,  H01L23/53209 ,  H01L23/53257 ,  H01L23/5329 ,  H01L21/76897

Abstract: Provided is a semiconductor chip architecture including a wafer, a front-end-of-line (FEOL) layer on a first side of the wafer, the FEOL layer including a semiconductor device and an interlayer dielectric (ILD) structure on the semiconductor device on the first side of the wafer, a shallow trench isolation (STI) structure in the wafer, and the wafer, a middle-of-line (MOL) layer provided on the first FEOL layer, the MOL layer including a contact and a via connected to the contact, an insulating layer on the first side of the wafer and adjacent to the via in a horizontal direction, a power rail penetrating the wafer from a second side of the wafer opposite to the first side, wherein the via extends through the ILD structure, the STI structure, and the wafer in a vertical direction to contact the power rail.

公开(公告)号：US20230049816A1

公开(公告)日：2023-02-16

申请号：US17504755

申请日：2021-10-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： SOOYOUNG PARK ,  Seunghyun Song ,  Byounghak Hong ,  Seungchan Yun

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/66

Abstract: Integrated circuit devices and methods of forming the same are provided. Integrated circuit devices may include a first channel layer including a first surface, a second channel layer that is spaced apart from the first channel layer in a first direction and includes a second surface, a first gate electrode and a second gate electrode. The first surface and the second surface may be spaced apart from each other in the first direction and may face opposite directions. The first channel layer may be in the first gate electrode, and the first gate electrode may be absent from the first surface of the first channel layer. The second channel layer may be in the second gate electrode, and the second gate electrode may be absent from the second surface of the second channel layer.

公开(公告)号：US11502167B2

公开(公告)日：2022-11-15

申请号：US17146136

申请日：2021-01-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byounghak Hong ,  Seunghyun Song ,  Kang Ill Seo ,  Hwichan Jun ,  Inchan Hwang

IPC: H01L29/06 ,  H01L27/092 ,  H01L29/423 ,  H01L29/786 ,  H01L29/417

Abstract: A semiconductor device include: a substrate; a 1st transistor formed above the substrate, the 1st transistor including a 1st channel set of a plurality of 1st nanosheet layers, a 1st gate structure surrounding the 1st nanosheet layers, and 1st and 2nd source/drain regions at both ends of the 1st channel set; and a 2nd transistor formed above the 1st transistor in a vertical direction, the 2nd transistor including a 2nd channel set of a plurality of 2nd nanosheet layers, a 2nd gate structure surrounding the 2nd nanosheet layers, and 3rd and 4th source/drain regions at both ends of the 2nd channel set, wherein the 1st channel set has a greater width than the 2nd channel set, wherein a number of the 1st nanosheet layers is smaller than a number of the 2nd nanosheet layers, and wherein a sum of effective channel widths of the 1st nanosheet layers is substantially equal to a sum of effective channel width of the 2nd nanosheet layers.

公开(公告)号：US11355640B1

公开(公告)日：2022-06-07

申请号：US17167640

申请日：2021-02-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byounghak Hong ,  Seunghyun Song

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/06

Abstract: A hybrid multi-stack semiconductor device and a method of manufacturing the same are provided. The hybrid multi-stack semiconductor device includes a nanosheet stack and a fin field-effect transistor (finFET) stack formed above the nanosheet stack, wherein the nanosheet stack includes a plurality of nanosheet layers formed above a substrate and enclosed by a 1st gate structure, wherein the at least one fin structure has a self-aligned form with respect to the nanosheet stack so that a left horizontal distance between a leftmost side surface of the at least one fin structure and a left side surface of the nanosheet stack is equal to a right horizontal distance between a rightmost side surface of the at least one fin structure and a right side surface of the nanosheet stack.

公开(公告)号：US12230571B2

公开(公告)日：2025-02-18

申请号：US17576007

申请日：2022-01-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gilhwan Son ,  Hoonseok Seo ,  Saehan Park ,  Byounghak Hong ,  Kang-Ill Seo

IPC: H01L23/528 ,  H01L21/74 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/48 ,  H01L23/485 ,  H01L23/535 ,  H01L27/088

Abstract: Methods of forming an integrated circuit devices may include forming a transistor on a first surface of a substrate. The transistor may include an active region, a source/drain region contacting the active region and a gate electrode on the active region. The methods may also include forming a conductive wire that is electrically connected to the source/drain region, forming a trench extending through the substrate by etching a second surface of the substrate, which is opposite the first surface of the substrate, and forming a power rail in the trench. The power rail is electrically connected to conductive wire.

公开(公告)号：US12040327B2

公开(公告)日：2024-07-16

申请号：US17500618

申请日：2021-10-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Inchan Hwang ,  Seunghyun Song ,  Byounghak Hong

IPC: H01L27/092 ,  H01L21/02 ,  H01L21/8238 ,  H01L23/535 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L27/0922 ,  H01L21/0259 ,  H01L21/823807 ,  H01L21/823871 ,  H01L23/535 ,  H01L27/0924 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/78696

Abstract: A multi-stack semiconductor device includes: a lower-stack transistor structure including a lower active region and a lower gate structure, the lower active region including a lower channel structure, and the lower gate structure surrounding the lower channel structure; an upper-stack transistor structure vertically stacked above the lower-stack transistor structure, and including an upper active region and an upper gate structure, the upper active region including an upper channel structure, and the upper gate structure surrounding the upper channel structure; and at least one gate contact plug contacting a top surface of the lower gate structure, wherein the lower gate structure and the upper gate structure have a substantially same size in a plan view, and wherein the lower gate structure is not entirely overlapped by the upper gate structure in a vertical direction.

公开(公告)号：US20240063123A1

公开(公告)日：2024-02-22

申请号：US18386497

申请日：2023-11-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Saehan PARK ,  Hoonseok Seo ,  Gil Hwan Son ,  Byounghak Hong ,  Kang Ill Seo

IPC: H01L23/528 ,  H01L27/06 ,  H01L23/48 ,  H01L21/768 ,  H01L21/822

CPC classification number: H01L23/5286 ,  H01L27/0694 ,  H01L23/481 ,  H01L21/76898 ,  H01L21/8221 ,  H01L23/53257

Abstract: Provided is a semiconductor architecture including a wafer, a first semiconductor device provided on a first surface of the wafer, the first semiconductor device being configured to route signals, a second semiconductor device provided on a second surface of the wafer opposite to the first surface of the wafer, the second semiconductor device being configured to supply power, and a buried power rail (BPR) included inside of the wafer and extending from the first surface of the wafer to the second surface of the wafer, the BPR being configured to deliver the power from the second semiconductor device to the first semiconductor device.

公开(公告)号：US20230411353A1

公开(公告)日：2023-12-21

申请号：US17969402

申请日：2022-10-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byounghak Hong ,  Wookhyun Kwon ,  Jaehong Lee

IPC: H01L25/065 ,  H01L23/528 ,  H01L27/02 ,  H01L27/06

CPC classification number: H01L25/0657 ,  H01L23/5286 ,  H01L27/0259 ,  H01L27/0688

Abstract: A (3D) stacked field effect transistors (SFETs) device includes a first transistor structure including a first source/drain (S/D) region and a second S/D region, the second S/D region including a first side and a second side facing opposite to the first side, and a second transistor structure including a third S/D region and a fourth S/D region, the fourth S/D region including a first side and a second side facing opposite to the first side. The first transistor structure and the second transistor structure are merged such that the second side of the second S/D region is merged with the first side of the fourth S/D region.