A (3D) stacked field effect transistors (SFETs) device includes a first transistor structure including a first source/drain (S/D) region and a second S/D region, the second S/D region including a first side and a second side facing opposite to the first side, and a second transistor structure including a third S/D region and a fourth S/D region, the fourth S/D region including a first side and a second side facing opposite to the first side. The first transistor structure and the second transistor structure are merged such that the second side of the second S/D region is merged with the first side of the fourth S/D region.