公开(公告)号：US20230275021A1

公开(公告)日：2023-08-31

申请号：US17738393

申请日：2022-05-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： BYOUNGHAK HONG ,  Jeonghyuk Yim ,  Inchan Hwang ,  Gilhwan Son ,  Seungyoung Lee ,  Saehan Park ,  Janggeun Lee ,  Myunghoon Jung ,  Seungchan Yun ,  Buhyun Ham ,  Kang-ILL Seo

IPC: H01L23/528 ,  H01L23/522 ,  H01L21/302 ,  H01L21/8234

CPC classification number: H01L23/5286 ,  H01L23/5283 ,  H01L23/5226 ,  H01L21/302 ,  H01L21/823475

Abstract: Integrated circuit devices may include a transistor, a passive device, a substrate extending between the transistor and the passive device and a power rail. The passive device may be spaced apart from the substrate. Each of the passive device and the power rail may have a first surface facing the substrate, and the first surface of the passive device is closer than the first surface of the power rail to the substrate.

公开(公告)号：US20240194768A1

公开(公告)日：2024-06-13

申请号：US18533262

申请日：2023-12-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Gilhwan Son ,  Taegon Kim ,  Sihyung Lee ,  Jihye Yi

IPC: H01L29/66 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/20 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/2003 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/785

Abstract: A method of manufacturing an integrated circuit device includes forming a preliminary channel stack, which includes sacrificial layers and channel layers, on a substrate, forming a preliminary channel pattern and a fin-type active region by removing a portion of the preliminary channel stack and a portion of the substrate to define a buried trench, forming a sacrificial buried layer in the buried trench, forming a source/drain region on the fin-type active region, forming, on the sacrificial buried layer, a power via electrically connected to the source/drain region, removing a portion of the substrate to expose a bottom surface of the sacrificial buried layer, removing the sacrificial buried layer and forming, in the buried trench, a backside buried wiring layer connected to the power via, and forming a backside wiring structure electrically connected to the backside buried wiring layer.

公开(公告)号：US12230571B2

公开(公告)日：2025-02-18

申请号：US17576007

申请日：2022-01-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gilhwan Son ,  Hoonseok Seo ,  Saehan Park ,  Byounghak Hong ,  Kang-Ill Seo

IPC: H01L23/528 ,  H01L21/74 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/48 ,  H01L23/485 ,  H01L23/535 ,  H01L27/088

Abstract: Methods of forming an integrated circuit devices may include forming a transistor on a first surface of a substrate. The transistor may include an active region, a source/drain region contacting the active region and a gate electrode on the active region. The methods may also include forming a conductive wire that is electrically connected to the source/drain region, forming a trench extending through the substrate by etching a second surface of the substrate, which is opposite the first surface of the substrate, and forming a power rail in the trench. The power rail is electrically connected to conductive wire.